SC68C652BIB48,157 NXP Semiconductors, SC68C652BIB48,157 Datasheet - Page 18

• Manufacturer Part Number: SC68C652BIB48,157
• Description: IC UART DUAL 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Voltage: 2.25 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278766157; SC68C652BIB48; SC68C652BIB48

NXP Semiconductors
SC68C652B_2
Product data sheet
7.3.1.1 Mode 0 (FCR bit 3 = 0)
7.3.1.2 Mode 1 (FCR bit 3 = 1)
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
7.3.1 DMA mode
7.3 FIFO Control Register (FCR)
When FCR[0] = logic 1, resetting IER[0:3] enables the SC68C652B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for transmit and/or receive data status. Since the receiver and transmitter
have separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready pin (TXRDYn) will go to a logic 0 whenever the FIFO
(THR, if FIFO is not enabled) is empty. Receive Ready pin (RXRDYn) will go to a logic 0
whenever the Receive Holding Register (RHR) is loaded with a character.
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardless of the programmed level until the FIFO is full. RXRDYn remains a logic 0 as
long as the FIFO fill level is above the programmed trigger level.
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LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
Rev. 02 — 2 November 2009
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
SC68C652B
© NXP B.V. 2009. All rights reserved.
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