SC16C852IBS,151 NXP Semiconductors, SC16C852IBS,151 Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
SC16C852IBS,151
Manufacturer Part Number
SC16C852IBS,151
Description
IC UART DUAL W/FIFO 32HVQFN
Manufacturer
NXP Semiconductors
Type
IrDAr
Datasheet
1.SC16C852IBS128.pdf
(60 pages)
Specifications of SC16C852IBS,151
Number Of Channels
2, DUART
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Features
Programmable
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
2.5 V ~ 3.3 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Voltage
1.65 V ~ 1.95 V
Data Rate
5 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.5 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935283099151 SC16C852IBS-S
NXP Semiconductors
SC16C852_1
Product data sheet
6.3 Internal registers
The SC16C852 provides two sets of internal registers (A and B) consisting of 25 registers
each for monitoring and controlling the functions of each channel of the UART. These
registers are shown in
Table 5.
[1]
[2]
[3]
[4]
[5]
[6]
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Second special register set (TXLVLCNT/RXLVLCNT)
0
1
Enhanced feature register set (EFR, Xon1/Xon2, Xoff1/Xoff2)
0
1
1
1
1
First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)
0
1
1
1
Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)
0
1
1
1
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Second special registers are accessible only when EFCR[0] = 1.
Enhanced feature registers are only accessible when LCR = 0xBF.
First extra feature registers are only accessible when EFCR[2:1] = 01b.
Second extra feature registers are only accessible when EFCR[2:1] = 10b.
A1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
Internal registers decoding
A0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
Read mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Transmit FIFO Level Count
Receive FIFO Level Count
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Flow Control Count High
Flow Control Count Low
Clock Prescaler
RS-485 turn-around Timer
Additional Feature Control Register 2 Additional Feature Control Register 2
Additional Feature Control Register 1 Additional Feature Control Register 1
Rev. 01 — 31 August 2009
Table
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
5.
[2]
[3]
Write mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Extra Feature Control Register (EFCR)
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
n/a
n/a
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Flow Control Count High
Flow Control Count Low
Clock Prescaler
RS-485 turn-around Timer
[4]
SC16C852
[1]
© NXP B.V. 2009. All rights reserved.
[6]
[5]
12 of 60