SC16C852IBS,151 NXP Semiconductors, SC16C852IBS,151 Datasheet - Page 29
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SC16C852IBS,151
Manufacturer Part Number
SC16C852IBS,151
Description
IC UART DUAL W/FIFO 32HVQFN
Manufacturer
NXP Semiconductors
Type
IrDAr
Datasheet
1.SC16C852IBS128.pdf
(60 pages)
Specifications of SC16C852IBS,151
Number Of Channels
2, DUART
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Features
Programmable
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
2.5 V ~ 3.3 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Voltage
1.65 V ~ 1.95 V
Data Rate
5 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.5 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935283099151 SC16C852IBS-S
NXP Semiconductors
SC16C852_1
Product data sheet
7.4 Interrupt Status Register (ISR)
The SC16C852 provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits.
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 15.
Table 16.
Priority
level
1
2
2
3
4
5
6
Bit
7:6
5:4
3:1
0
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
ISR[5]
0
0
0
0
0
0
1
Interrupt source
Interrupt Status Register bits description
ISR[4]
0
0
0
0
0
1
0
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C852 mode.
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see
INT status.
Rev. 01 — 31 August 2009
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
ISR[3]
0
0
1
0
0
0
0
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
Table 15 “Interrupt source”
ISR[0]
0
0
0
0
0
0
0
Table
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/
Special character
CTS, RTS change of state
15).
SC16C852
© NXP B.V. 2009. All rights reserved.
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