SC16C852IBS,151 NXP Semiconductors, SC16C852IBS,151 Datasheet - Page 36
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SC16C852IBS,151
Manufacturer Part Number
SC16C852IBS,151
Description
IC UART DUAL W/FIFO 32HVQFN
Manufacturer
NXP Semiconductors
Type
IrDAr
Datasheet
1.SC16C852IBS128.pdf
(60 pages)
Specifications of SC16C852IBS,151
Number Of Channels
2, DUART
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Features
Programmable
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
2.5 V ~ 3.3 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Voltage
1.65 V ~ 1.95 V
Data Rate
5 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.5 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935283099151 SC16C852IBS-S
NXP Semiconductors
SC16C852_1
Product data sheet
7.15 Transmit Interrupt Level register (TXINTLVL)
7.16 Receive Interrupt Level register (RXINTLVL)
Table 26.
[1]
This 8-bit register is used to store the transmit FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1.
Table 27.
[1]
This 8-bit register is used to store the receive FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1.
Table 28.
Cont-3
0
1
0
1
X
X
X
1
0
1
Bit
7:0
Bit
7:0
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
For 32-byte FIFO mode, refer to
Table 27
Table 28
Symbol
TXINTLVL[7:0]
Symbol
RXINTLVL[7:0]
Cont-2
0
0
1
1
X
X
X
0
1
1
Software flow control functions
TXINTLVL register bits description
RXINTLVL register bits description
shows TXINTLVL register bit settings.
shows RXINTLVL register bit settings.
Cont-1
X
X
X
X
0
1
0
1
1
1
Rev. 01 — 31 August 2009
Description
This register stores the programmable transmit interrupt trigger levels
for 128-byte FIFO mode
Description
This register stores the programmable receive interrupt trigger levels
for 128-byte FIFO mode
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Cont-0
X
X
X
X
0
0
1
1
1
1
Section
7.3.
TX, RX software flow controls
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
[1]
[1]
[1]
.
.
SC16C852
© NXP B.V. 2009. All rights reserved.
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