SC28L91A1A,512 NXP Semiconductors, SC28L91A1A,512 Datasheet - Page 18

• Manufacturer Part Number: SC28L91A1A,512
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L91A1A,512

• Features: False-start Bit Detection
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935267418512; SC28L91A1A; SC28L91A1A

OP7. The data source for output ports OP0 and OP1 is controlled by
These pins along with the IP pins and their change of state detectors
If the transmitter is disabled it continues operating until the character
Philips Semiconductors
“just missed” and the first change-of-state is not detected until 25 s
later.
Output Port
The output ports are controlled from six places: the OPCR, OPR,
MR, Command, SOPR and ROPR registers. The OPCR register
controls the source of the data for the output ports OP2 through
the MR and CR registers. When the OPR is the source of the data
for the output ports, the data at the ports is inverted from that in the
OPR register. The content of the OPR register is controlled by the
“Set Output Port Bits Command” and the “Reset Output Bits
Command”. These commands are at E and F, respectively. When
these commands are used, action takes place only at the bit
locations where ones exist. For example, a one in bit location 5 of
the data word used with the “Set Output Port bits” command will
result in OPR[5] being set to one. The OP5 would then be set to
zero (V
associated with the “Reset Output Ports Bits” command would set
OPR[5] to zero and, hence, the pin OP5 to a one (V
are often used for modem and DMA control.
OPERATION
Transmitter
The SC28L91 is conditioned to transmit data when the transmitter is
enabled through the command register. The SC28L91 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP6 or OP7 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMPT bits will be
set in the status register. When a character is loaded to the transmit
FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1)
the transmit FIFO is empty and the transmit shift register has
finished transmitting the stop bit of the last character written to the
transmit FIFO, or 2) the transmitter is disabled and then re-enabled.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the TxFIFO.
currently being transmitted and any characters in the TxFIFO,
including parity and stop bits, have been transmitted. New data
cannot be loaded to the TxFIFO when the transmitter is disabled.
When the transmitter is reset it stops sending data immediately.
The transmitter can be forced to send a break (a continuous low
condition) by issuing a START BREAK command via the CR
register. The break is terminated by a STOP BREAK command or a
transmitter reset.
2004 Oct 21
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
SS
). Similarly, a one in bit position 5 of the data word
DD
).
18
the character transmitted. If it is found to be High, the transmitter will
MR2[5]. When this mode of operation is set, the meaning of the OP0
loaded into the RxFIFO and the received break bit in the SR is set to
If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1
must be Low in order for the character to be transmitted. The
transmitter will check the state of the CTS input at the beginning of
delay the transmission of any following characters until the CTS has
returned to the low state. CTS going high during the serialization of
a character will not affect that character.
The transmitter can also control the RTSN outputs, OP0 or OP1 via
or OP1 signals will usually be ‘end of message’. See description of
the MR2[5] bit for more detail. This feature may be used to
automatically “turn around” a transceiver in simplex systems.
Receiver
The SC28L91 is conditioned to receive data when enabled through
the command register. The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled the 16X
clock for 7–1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled high, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still Low, a valid start bit is assumed and the receiver continues to
sample the input at one-bit time intervals at the theoretical center of
the bit. When the proper number of data bits and parity bit (if any)
have been assembled, and one/half stop bit has been detected the
byte is loaded to the RxFIFO. The least significant bit is received
first. The data is then transferred to the Receive FIFO and the
RxRDY bit in the SR is set to a 1. This condition can be
programmed to generate an interrupt at OP4 or OP5 and INTRN. If
the character length is less than 8 bits, the most significant unused
bits in the RxFIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However if a framing error occurs (a non-zero
character was received without a stop bit) and then RxD remains
low one/half bit time the receiver operates as if a new start bit was
detected. It then continues to assemble the next character.
The parity error, framing error, and overrun error (if any) are strobed
into the SR from the next byte to be read from the Rx FIFO.
If a break condition is detected (RxD is Low for the entire character
including the stop bit), a character consisting of all zeros will be
1. The RxD input must return to high for two (2) clock edges of the
X1 crystal clock for the receiver to recognize the end of the break
condition and begin the search for a start bit.
This will usually require a high time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to the X1
clock.
Transmitter Reset and Disable
Note the difference between transmitter disable and reset. A
transmitter reset stops transmitter action immediately, clears the
transmitter FIFO and returns the idle state. A transmitter disable
withdraws the transmitter interrupts but allows the transmitter to
continue operation until all bytes in its FIFO and shift register have
been transmitted including the final stop bits. It then returns to its
idle state.
Receiver FIFO
The RxFIFO consists of a First-In-First-Out (FIFO) stack with a
capacity of 8 or 16 characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
SC28L91
Product data sheet