SC28L91A1A,512 NXP Semiconductors, SC28L91A1A,512 Datasheet - Page 21

• Manufacturer Part Number: SC28L91A1A,512
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L91A1A,512

• Features: False-start Bit Detection
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935267418512; SC28L91A1A; SC28L91A1A

Philips Semiconductors
Table 2. Condensed Register bit formats
2004 Oct 21
Register Acronyms and Read / Write Capability
(R/W = Read/Write, R = Read only, W = Write only)
Mode Register
Status Register
Clock Select
Command Register
Receiver FIFO
Transmitter FIFO
Input Port Change Register
Auxiliary Control Register
Interrupt Status Register
N
MR0
MR1
MR2
CSR
SR
CR
RxFIFO
TxFIFO
IPCR
ACR
ISR
IMR
CTU
CTPU
CTL
CTPL
IPR
OPCR
Strt C/T
SOPR
Stp C/T
ROPR
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
ame
Adr
0
0
0
1
1
2
3
3
4
4
5
5
6
6
7
7
D
D
E
E
F
F
Bit 7
WATCH
DOG
RxRTS
Control
Channel Mode
Receiver Clock, Select Code
Received
Break
Channel Command codes
Read 8 bits from Rx FIFO
Write 8 bits to Tx FIFO
Delta IP3
Baud Group Counter Timer mode and clock select
Change
Input Port
Change
Input Port
Read 8 MSb of the BRG Timer divisor.
Write 8 MSb of the BRG Timer divisor.
Read 8 LSb of the BRG Timer divisor.
Write 8 LSb of the BRG Timer divisor.
State of IP
Configure
OP7
Read Address E to start Counter Timer
Set OP 7
Read Address F to stop counter Timer
Reset OP 7
Bit 6
RxINT BIT 2
RxINT BIT 1
Framing
Error
Delta IP2
Ignore in ISR Reads
Set to 0
State of IP 6
Configure
OP6
Set OP 6
Reset OP 6
MRn
SR
CSR
CR
RxFIFO
RxFIFO
IPCR
ACR
ISR
Bit 5
TxINT [1:0]
Error Mode
TxRTS
Control
Parity Error
Delta IP1
Set to 0
State of IP 5
Configure
OP5
Set OP 5
Reset OP 5
R/W
R
W
W
R
W
R
W
R
Bit 4
Parity Mode
CTSN Enable
Tx
Overrun Error
Delta IP0
Set to 0
State of IP 4
Configure
OP4
Set OP 4
Reset OP 4
21
Interrupt Mask Register
Counter Timer Upper Value
Counter Timer Lower Value
Counter Timer Preset Upper
Counter Timer Preset Lower
Input Port Register
Output Configuration Register
Set Output Port
Reset Output Port
Interrupt vector or GP register
Bit 3
FIFO SIZE
Stop Bit Length
Transmitter Clock select code,
TxEMT
Disable Tx
State of IP3
Enable IP3
Counter
Ready
Counter
Ready
State of IP 3
Configure OP3
Set OP 3
Reset OP 3
BAUD RATE
Bit 2
EXTENDED
II
Parity Type
TxRDY
Enable Tx
State of IP2
Enable IP2
Change
Break
Change
Break
State of IP 2
Set OP 2
Reset OP 2
Bit 1
TEST 2
Bits per Character
RxFULL
Disable Rx
State of IP1
Enable IP1
RxRDY
RxRDY
State of IP1
Configure OP2
Set OP 1
Reset OP 1
IMR
CTU
CTL
CTPU
CTPL
IPR
OPCR
Bits
Bits
IVR/GP
SC28L91
Product data sheet
Bit 0
BAUD RATE
EXTENDED 1
RxRDY
Enable Rx
State of IP0
Enable IP0
TxRDY
TxRDY
State of IP 0
Set OP 0
Reset OP 0
W
R
R
W
W
R
W
W
W
R/W