SC28L91A1A,512 NXP Semiconductors, SC28L91A1A,512 Datasheet - Page 24

• Manufacturer Part Number: SC28L91A1A,512
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L91A1A,512

• Features: False-start Bit Detection
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935267418512; SC28L91A1A; SC28L91A1A

Add 0.5 to values shown for 0–7 if channel is programmed for 5 bits/char.
Philips Semiconductors
MR2 – Mode Register 2
MR2 is accessed when the MR pointer points to MR2, which occurs after any access to MR1. Accesses to MR2 do not change the pointer.
NOTE:
MR2[7:6]— Mode Select
The channel of the UART can operate in one of four modes.
MR2[7:6] = 00 is the normal mode, with the transmitter and receiver
operating independently.
MR2[7:6] = 01 places the channel in the automatic echo mode,
which automatically retransmits the received data. The following
conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter needs not be
4. The TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for
6. Character framing is checked, but the stop bits are retransmitted
7. A received break is echoed as received until the next valid start
8. CPU to receiver communication continues normally, but the CPU
MR2[7:6] = 10 selects local loop back diagnostic mode. In this
mode:
1. The transmitter output is internally connected to the receiver
2. The transmit clock is used for the receiver.
3. The TxD output is held High.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the receiver need not be
6. CPU to transmitter and receiver communications continue
MR2[7:6] = 11 selects remote loop back diagnostic mode. In this
mode:
1. Received data is reclocked and retransmitted on the TxD
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
2004 Oct 21
ADDR
MR
0x00
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
enabled.
transmission, i.e. transmitted parity bit is as received.
as received.
bit is detected.
to transmitter link is disabled.
input.
enabled.
normally.
out–put.
conditions are inactive.
BIT 7
CHANNEL MODE
10 = Local loop
11 = Remote loop
00 = Normal
01 = Auto-Echo
BIT 6
BIT 5
Tx CONTROLS
RTS
0 = No
1 = Yes
BIT 4
CTS
ENABLE Tx
0 = No
1 = Yes
24
may be very long compared to bus cycles. If rapid reconfiguration of
This feature can be used to automatically terminate the transmission
4. The received parity is not checked and is not regenerated for
5. The receiver must be enabled.
6. Character framing is not checked, and the stop bits are
7. A received break is echoed as received until the next valid start
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately.
An exception to this occurs when switching out of auto echo or
remote loop back modes. If the de-selection occurs just after the
receiver has sampled the stop bit (indicated in auto echo by
assertion of RxRDY) and the transmitter is enabled, then the
transmitter will remain in auto echo mode until the stop bit(s) have
been re-transmitted.
In most situations the above is rendered transparent by other
system considerations. However recall that the stop bit sequence
the transmitter is desired in the above conditions the controlling
system should wait for the TxEMT bit to set or issue a Tx software
reset before reconfiguration begins.
MR2[5]— Transmitter Request–to–Send Control
This bit controls the deactivation of the RTSN output (OP0) by the
transmitter. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR2[5] = 1 caused OPR[0] to be
reset automatically one bit time after the characters in the transmit
shift register and in the TxFIFO, if any, are completely transmitted
including the programmed number of stop bits, if the transmitter is
not enabled.
of a message as follows (“line turnaround”):
1. Program auto–reset mode: MR2[5] = 1.
2. Enable transmitter.
3. Asset RTSN: OPR[0] = 1.
4. Send message.
5. Disable transmitter after the last character is loaded into the
BIT 3
STOP BIT LENGTH
NOTE: Add 0.5 to binary codes 0–7 for 5 bit character lengths.
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
transmission, i.e., transmitted parity is as received.
retransmitted as received.
bit is detected.
TxFIFO.
BIT 2
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
BIT 1
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
SC28L91
Product data sheet
BIT 0
C = 1.813
D = 1.875
E = 1.938
F = 2.000