SC28L91A1A,512 NXP Semiconductors, SC28L91A1A,512 Datasheet - Page 27

• Manufacturer Part Number: SC28L91A1A,512
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L91A1A,512

• Features: False-start Bit Detection
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935267418512; SC28L91A1A; SC28L91A1A

Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
Philips Semiconductors
CR—Command Register
CR is a register used to supply commands to the UART. Multiple
commands can be specified in a single write to CR as long as the
commands are non–conflicting, e.g., the ‘enable transmitter’ and
CR COMMAND REGISTER
NOTES:
CR[7:4]—Miscellaneous Commands
Execution of the commands in the upper four bits of this register
must be separated by 3 X1 clock edges. Other reads or writes
(including writes to the lower four bits) may be inserted to achieve
this separation.
CR[7:4]—Commands
2004 Oct 21
Addr
CR
0x02
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
No command.
Reset MR pointer. Causes the MR pointer to point to
MR1.
Reset receiver. Resets the receiver as if a hardware
reset had been applied. The receiver is disabled and
the FIFO is flushed.
Reset transmitter. Resets the transmitter as if a hard-
ware reset had been applied.
Reset error status. Clears the Received Break, Parity
Error, and Overrun Error bits in the status register
(SR[7:4]). Used in character mode to clear OE status
(although Received Break, PE and FE bits will also be
cleared) and in block mode to clear all error status after
a block of data has been received.
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be
cleared to zero
Start break. Forces the TxD output Low (spacing). If the
transmitter is empty the start of the break condition will
be delayed up to two bit times. If the transmitter is ac-
tive the break begins when transmission of the charac-
ter is completed. If a character is in the TxFIFO, the
start of the break will be delayed until that character, or
any other loaded subsequently are transmitted. The
transmitter must be enabled for this command to be
accepted.
Stop break. The TxD line will go High (marking) within
two bit times. TxD will remain High for one bit time be-
fore the next character, if any, is transmitted.
Assert RTSN. Causes the RTSN output to be asserted
(Low).
Negate RTSN. Causes the RTSN output to be negated
(High)
Set Timeout Mode On. The receiver in this channel will
restart the C/T as the receive character is transferred
from the shift register to the RxFIFO. The C/T is placed
in the counter mode, the START/STOP counter com-
mands are disabled, the counter is stopped, and the
Counter Ready Bit, ISR[3], is reset. (See also Watch-
dog timer description in the receiver section.)
Bit 7
MISCELLANEOUS COMMANDS
See Text of Channel Command Register
BIT 6
BIT 5
BIT 4
27
character being received will be lost. The command has no effect on
Enables operation of the receiver. If not in the special wakeup mode,
‘reset transmitter’ commands cannot be specified in a single
command word.
CR[3]—Disable Transmitter
This command terminates transmitter operation and reset the
TxRDY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the TxFIFO when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
CR[2]—Enable Transmitter
Enables operation of the transmitter. The TxRDY and TxEMT status
bits will be asserted if the transmitter is idle.
CR[1]—Disable Receiver
This command terminates operation of the receiver immediately—a
the receiver status bits or any other control registers. If the special
multi-drop mode is programmed, the receiver operates even if it is
disabled. See Operation section.
CR[0]—Enable Receiver
this also forces the receiver into the search for start–bit state.
1011
1100
1101
1110
1111
BIT 3
Disable Tx
1 = Yes
0 = No
Set MR pointer to ‘0’
Disable Timeout Mode. This command returns control
of the C/T to the regular START/STOP counter com-
mands. It does not stop the counter, or clear any pend-
ing interrupts. After disabling the timeout mode, a ‘Stop
Counter’ command should be issued to force a reset of
the ISR[3] bit
Not used.
Power Down Mode On. In this mode, the UART oscilla-
tor is stopped and all functions requiring this clock are
suspended. The execution of commands other than
disable power down mode (1111) requires a X1/CLK.
While in the power down mode, do not issue any com-
mands to the CR except the disable power down mode
command. The contents of all registers will be saved
while in this mode. It is recommended that the transmit-
ter and receiver be disabled prior to placing the UART
into power down mode.
Disable Power Down Mode. This command restarts the
oscillator. After invoking this command, wait for the os-
cillator to start up before writing further commands to
the CR.
BIT 2
Enable Tx
1 = Yes
0 = No
BIT 1
Disable Rx
1 = Yes
0 = No
SC28L91
Product data sheet
BIT 0
Enable Rx
1 = Yes
0 = No