XR20M1172IG28-F Exar Corporation, XR20M1172IG28-F Datasheet - Page 27

• Manufacturer Part Number: XR20M1172IG28-F
• Description: IC UART FIFO I2C/SPI 64B 28TSSOP
• Manufacturer: Exar Corporation

Specifications of XR20M1172IG28-F

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TSSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1298-5

0x0C IOIntEna RD/WR
0x0D reserved
0x0B
0x0E IOControl RD/WR
0x0F
A
0x02
0x06
REV. 1.0.1
SEE”RECEIVER” ON PAGE 17.
SEE”TRANSMITTER” ON PAGE 15.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
0x00
0x01
0x02
0x04
0x05
0x07
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
DDR
IOState
XOFF1
XOFF2
T
EFCR
XON1
XON2
N
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
DLM
DLD
EFR
R
DLL
ABLE
AME
EG
IER versus Receive FIFO Interrupt Mode Operation
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Fast IR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
R
W
EAD
RITE
-
/
Enable
Mode
B
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
0
-7
Auto RTS
Enable
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
IT
0
0
0
-6
Baud Rate Generator Divisor
4X Mode 8X Mode
Special
RS485
Select
Invert
B
Enhanced Registers
Char
Bit-5
Bit-5
Auto
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
IT
0
0
-5
MCR[7:5],
IER [7:4],
ISR [5:4],
FCR[5:4],
RS485
Enable
Enable
27
B
Bit-4
Bit-4
Auto
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
DLD
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
IT
0
0
-4
S
HADED BITS ARE ENABLED WHEN
Divisor
UART
Reset
tional
B
Frac-
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
SW
IT
0
0
-3
GPIO or
IO Ch B
Modem
Disable
Divisor
tional
B
Frac-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Soft-
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
TX
IT
0
-2
GPIO or
IO Ch A
Modem
Disable
Divisor
tional
B
Frac-
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
RX
IT
0
-1
IOLatch
Divisor
Mode
B
Frac-
tional
Bit-0
Bit-0
9-Bit
Bit-0
Bit-0
Bit-0
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
EFR B
Cntl
IT
0
XR20M1172
-0
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR=0
C
LCR[7]=1
LCR[7]=1
EFR[4]=1
OMMENT
X
BF