XR20M1172IG28-F Exar Corporation, XR20M1172IG28-F Datasheet - Page 31

• Manufacturer Part Number: XR20M1172IG28-F
• Description: IC UART FIFO I2C/SPI 64B 28TSSOP
• Manufacturer: Exar Corporation

Specifications of XR20M1172IG28-F

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TSSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1298-5

REV. 1.0.1
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of spaces in the FIFO is above the selected trigger level, or when it gets empty in case that the FIFO
did not get filled over the trigger level on last re-load.
transmit interrupt when the number of available spaces in the FIFO is less than the transmit trigger level.
Table 10
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO is greater than the receive trigger level or when a receive data
timeout occurs (see
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
shows the selections.
“Section 2.8, Receiver” on page
T
ABLE
B
FCR
IT
0
0
1
1
-7
10: T
B
FCR
RANSMIT AND
IT
0
1
0
1
-6
B
FCR
IT
0
0
1
1
-5
R
ECEIVE
BIT
FCR
0
1
0
1
-4
31
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
Table 10
17).
FIFO T
T
(
RIGGER
CHARACTERS
R
ECEIVE
16
56
60
8
RIGGER
shows the selections. The UART will issue a
L
EVEL
)
L
T
EVEL
RIGGER
T
(
SPACES
RANSMIT
S
16
32
56
8
ELECTION
L
EVEL
)
XR20M1172