XRP7740ILB-F Exar Corporation, XRP7740ILB-F Datasheet - Page 15

• Manufacturer Part Number: XRP7740ILB-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Type: Step-Down (Buck)r

Specifications of XRP7740ILB-F

• Number Of Outputs: 5
• Package / Case: 40-WFQFN Exposed Pad
• Topology: Step-Down (Buck) (4), Linear (1)
• Function: Standby Power and GPIOs
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: 0.9 V ~ 5.1 V, 5A
• Voltage/current - Output 2: 0.9 V ~ 5.1 V, 15A
• Voltage/current - Output 3: 0.9 V ~ 5.1 V, 5A
• W/led Driver: No
• W/supervisor: Yes
• W/sequencer: No
• Voltage - Supply: 6.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Current - Output: 5A, 15A
• Voltage - Output: 0.9 ~ 5.1 V
• Voltage - Input: 6.5 ~ 20 V
• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Switching Frequency: 300 KHz to 1500 KHz
• Operating Supply Voltage: 6.5 V to 20 V
• Supply Current: 50 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Output Voltage: 0.9 V to 5.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 1016-1352 - EVAL BOARD FOR XRP77401016-1344 - IN-SOCKET PROG BRD VIA USB/GUI
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1353

REV 1.1.0
Chip Power-Up
The figure below shows the power-up sequence of XRP7740 during the normal operation. The startup stage is
divided into three phases. The first phase is the internal LDO power-up phase. The second phase is the
configuration transfer phase. The third phase is chip ready phase. The power up sequence is less than 1ms.
Internal LDO Power-Up Phase – Phase 1
When the ENABLE pin is set, internal VCC and VDD power up upon the power up of VIN1. Once the bandgap
reference is stable and VCC and VDD fall into the acceptable range, an internal VDDOK flag is generated. A
SYS_RESET remains low for a few clock cycles to reset all the internal registers. After that the internal
CONFIGURATION_TRANSFER signal raises high and the chip transits to the second phase.
Configuration Transfer Phase – Phase 2
In this phase, the contents in the configuration memory are transferred to the internal registers. The internal
oscillator switches to the programed switching frequency. The GPIO pins are properly configured as either inputs
or outputs. If the chip is programmed to run in the I
and SCL for the I
GPIO4 and GPIO5 respectively.
Chip Ready Phase – Phase 3
In this phase, the chip is ready for normal operation. An internal CHIP_READY flag goes high and enables the I
to acknowledge the Host’s serial commands. Channels that are configured as always-on channels are enabled.
Channels that are configured to be enabled by GPIOs are also enabled if the respective GPIO is asserted.
ENABLE_PIN
VIN1
VCC
VDD
VDDOK
SYS_RESET
CONFIG_TRANSFER
CHIP_READY
2
C bus. If chip is programmed to run in the NON-I
EXAR CONFIDENTIAL, PRELIMINARY & PROPRIETARY. DO NOT DISTRIBUTE OR COPY.
EXAR RESERVES THE RIGHT TO MAKE CHANGES TO THIS DATASHEET.
Phase 1
Power up sequence
Quad-Output Digital PWM Buck Controller
2
C mode, GPIO4 and GPIO5 are configured to serve as SDA
15
Phase 2
2
C mode, then these two pins can be used as
Phase 3
XRP7740
2
C