SX1212IWLTRT Semtech, SX1212IWLTRT Datasheet - Page 61

• Manufacturer Part Number: SX1212IWLTRT
• Description: IC TXRX 300MHZ-510MHZ 32-TQFN
• Manufacturer: Semtech

Specifications of SX1212IWLTRT

• Frequency: 300MHz ~ 510MHz
• Data Rate - Maximum: 150kbps
• Modulation Or Protocol: FSK, OOK
• Applications: AMR, ISM, Home Automation, Process Control
• Power - Output: 12.5dBm
• Sensitivity: -110dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK/OOK
• Package Type: TQFN EP
• Operating Supply Voltage (min): 2.1V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: SX1212IWLTR

Rev 2 – June 18th, 2009
ADVANCED COMMUNICATIONS & SENSING
Tx_irq_1
Fifofull
/Fifoempty
Fifo_fill_method
Fifo_fill
Tx_done
Fifo_overrun_clr
Res
RSSI_irq
PLL_locked
PLL_lock_en
RSSI_irq_thresh
2
1
0
7
6
5
4
3
2
1
0
7-0
13
13
13
14
14
14
13
14
14
14
14
15
r/w
r
r
r/w
r/w/
c
r
r/w/
c
r/w
r/w/
c
r/w/
c
r/w
IRQ_1 source in Tx mode:
If Data_mode(1:0) = 00 (Continuous mode):
x
If Data_mode(1:0) = 01 (Buffered mode) or 1x (Packet mode):
0
1
Fifofull IRQ source
Goes high when FIFO is full.
/Fifoempty IRQ source
Goes low when FIFO is empty
FIFO filling method (Buffered mode only):
0
1
FIFO filling status/control (Buffered mode only):
Goes high when FIFO is being filled (sync word has been detected)
Writing ‘1’ clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)
0
1
Tx_done IRQ source
Goes high when the last bit has left the shift register.
Goes high when an overrun error occurred.
Writing a 1 anytime clears flag (if set) and launches a new Rx or Tx process
(d): “0”, should be set to “1”.
Note: “0” disables the RSSI IRQ source. It can be left enabled at any time, and
the user can choose to map this interrupt to IRQ0/IRQ1 or not.
RSSI IRQ source:
Goes high when a signal above RSSI_irq_thresh is detected
Writing ‘1’ clears the bit
PLL status:
0
1
Writing a ‘1’ clears the bit
PLL_lock detect flag mapped to pin 23:
0
1
RSSI threshold for interrupt (coded as RSSI)
(d): “00000000”
DCLK
If Fifo_fill_method = ‘0’: (d)
If Fifo_fill_method = ‘1’:
Fifofull (d)
Tx_done
Automatically starts when a sync word is detected (d)
Manually controlled by Fifo_fill
Stop filling the FIFO
Start filling the FIFO
not locked
locked
Lock detect disabled, pin 23 is HI
Lock detect enabled(d)
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