MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 112
![IC MIFARE HS READER 32-SOIC](/photos/7/0/70098/568-32-soic_sot287-1_sml.jpg)
MFRC53101T/0FE,112
Manufacturer Part Number
MFRC53101T/0FE,112
Description
IC MIFARE HS READER 32-SOIC
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Specifications of MFRC53101T/0FE,112
Rf Type
Read Only
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B, ISO15693
Package / Case
32-SOIC (0.300", 7.50mm Width)
Product
RFID Readers
Operating Temperature Range
- 25 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2224-5
935269691112
MFRC531
MFRC53101TD
935269691112
MFRC531
MFRC53101TD
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MFRC53101T/0FE,112
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
Table 70. TxControl register bit descriptions . . . . . . . . . .57
Table 71. CwConductance register (address: 12h) reset
Table 72. CwConductance register bit descriptions . . . .58
Table 73. ModConductance register (address: 13h) reset
Table 74. ModConductance register bit descriptions . . . .58
Table 75. CoderControl register (address: 14h) reset value:
Table 76. CoderControl register bit descriptions . . . . . . .59
Table 77. ModWidth register (address: 15h) reset value:
Table 78. ModWidth register bit descriptions . . . . . . . . . .59
Table 79. PreSet16 register (address: 16h) reset value:
Table 80. TypeBFraming register (address: 17h) reset
Table 81. TypeBFraming register bit descriptions . . . . . .60
Table 82. RxControl1 register (address: 19h) reset value:
Table 83. RxControl1 register bit descriptions . . . . . . . . .61
Table 84. DecoderControl register (address: 1Ah) reset
Table 85. DecoderControl register bit descriptions . . . . .62
Table 86. BitPhase register (address: 1Bh) reset value:
Table 87. BitPhase register bit descriptions . . . . . . . . . .62
Table 88. RxThreshold register (address: 1Ch) reset value:
Table 89. RxThreshold register bit descriptions . . . . . . .63
Table 90. BPSKDemControl register (address: 1Dh) reset
Table 91. BPSKDemControl register bit descriptions . . .63
Table 92. RxControl2 register (address: 1Eh) reset value:
Table 93. RxControl2 register bit descriptions . . . . . . . . .64
Table 94. ClockQControl register (address: 1Fh) reset
Table 95. ClockQControl register bit descriptions . . . . . .64
Table 96. RxWait register (address: 21h) reset value: 0000
Table 97. RxWait register bit descriptions . . . . . . . . . . . .65
Table 98. ChannelRedundancy register (address: 22h)
Table 99. ChannelRedundancy bit descriptions . . . . . . .65
Table 100. CRCPresetLSB register (address: 23h) reset
Table 101. CRCPresetLSB register bit descriptions . . . . .66
Table 102. CRCPresetMSB register (address: 24h) reset
Table 103. CRCPresetMSB bit descriptions . . . . . . . . . . .66
MFRC531_34
Product data sheet
PUBLIC
value: 0011 1111b, 3Fh bit allocation . . . . . . . .58
value: 0011 1111b, 3Fh bit allocation . . . . . . . .58
0001 1001b, 19h bit allocation . . . . . . . . . . . . .59
0001 0011b, 13h bit allocation . . . . . . . . . . . . .59
0000 0000b, 00h bit allocation . . . . . . . . . . . . .59
value: 0011 1011b, 3Bh bit allocation . . . . . . .60
0111 0011b, 73h bit allocation . . . . . . . . . . . . .61
value: 0000 1000b, 08h bit allocation . . . . . . .62
1010 1101b, ADh bit allocation . . . . . . . . . . . .62
1111 1111b, FFh bit allocation . . . . . . . . . . . . .63
value: 0001 1110b, 1Eh bit allocation . . . . . . .63
0100 0001b, 41h bit allocation . . . . . . . . . . . . .64
value: 000x xxxxb, xxh bit allocation . . . . . . . .64
0101b, 06h bit allocation . . . . . . . . . . . . . . . . .65
reset value: 0000 0011b, 03h bit allocation . . .65
value: 0101 0011b, 63h bit allocation . . . . . . .66
value: 0101 0011b, 63h bit allocation . . . . . . .66
Rev. 3.4 — 26 January 2010
056634
Table 104. PreSet25 register (address: 25h) reset value:
Table 105. MFOUTSelect register (address: 26h) reset
Table 106. MFOUTSelect register bit descriptions . . . . . 67
Table 107. PreSet27 (address: 27h) reset value: xxxx xxxxb,
Table 108. FIFOLevel register (address: 29h) reset value:
Table 109. FIFOLevel register bit descriptions . . . . . . . . 68
Table 110. TimerClock register (address: 2Ah) reset value:
Table 111. TimerClock register bit descriptions . . . . . . . . 68
Table 112. TimerControl register (address: 2Bh) reset value:
Table 113. TimerControl register bit descriptions . . . . . . . 69
Table 114. TimerReload register (address: 2Ch) reset value:
Table 115. TimerReload register bit descriptions . . . . . . . 69
Table 116. IRQPinConfig register (address: 2Dh) reset value:
Table 117. IRQPinConfig register bit descriptions . . . . . . 70
Table 118. PreSet2E register (address: 2Eh) reset value:
Table 119. PreSet2F register (address: 2Fh) reset value:
Table 120. Reserved registers (address: 31h, 32h, 33h, 34h,
Table 121. Reserved register (address: 39h) reset value:
Table 122. TestAnaSelect register (address: 3Ah) reset
Table 123. TestAnaSelect bit descriptions . . . . . . . . . . . . 71
Table 124. Reserved register (address: 3Bh) reset value:
Table 125. Reserved register (address: 3Ch) reset value:
Table 126. TestDigiSelect register (address: 3Dh) reset
Table 127. TestDigiSelect register bit descriptions . . . . . 72
Table 128. Reserved register (address: 3Eh, 3Fh) reset
Table 129. MFRC531 commands overview . . . . . . . . . . . 73
Table 130. StartUp command 3Fh . . . . . . . . . . . . . . . . . . 75
Table 131. Idle command 00h . . . . . . . . . . . . . . . . . . . . . 75
Table 132. Transmit command 1Ah . . . . . . . . . . . . . . . . . 76
Table 133. Transmission of frames of more than
Table 134. Receive command 16h . . . . . . . . . . . . . . . . . 79
Table 135. Return values for bit-collision positions . . . . . 81
0000 0000b, 00h bit allocation . . . . . . . . . . . . 66
value: 0000 0000b, 00h bit allocation . . . . . . . 67
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 67
0000 1000b, 08h bit allocation . . . . . . . . . . . . 68
0000 0111b, 07h bit allocation . . . . . . . . . . . . . 68
0000 0110b, 06h bit allocation . . . . . . . . . . . . 69
0000 1010b, 0Ah bit allocation . . . . . . . . . . . . 69
0000 0010b, 02h bit allocation . . . . . . . . . . . . 70
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 70
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 70
35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 71
value: 0000 0000b, 00h bit allocation . . . . . . . 71
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 72
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 72
value: xxxx xxxxb, xxh bit allocation . . . . . . . . 72
value: xxxx xxxxb, xxh bit allocation . . . . . . . . 73
64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ISO/IEC 14443 reader IC
MFRC531
© NXP B.V. 2010. All rights reserved.
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