MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 56

• Manufacturer Part Number: MFRC53101T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53101T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2224-5; 935269691112; MFRC531; MFRC53101TD

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
10.5.2.8 BitFraming register
Adjustments for bit oriented frames.
Table 67.
Table 68.
Bit
Symbol
Access
Bit
7
6 to 4 RxAlign[2:0]
3
2 to 0 TxLastBits[2:0]
Symbol
0
0
BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
BitFraming register bit descriptions
R/W
7
0
Rev. 3.4 — 26 January 2010
Value
-
000
001
...
111
-
-
6
056634
RxAlign[2:0]
Description
reserved
defines the bit position for the first bit received to be stored in
the FIFO buffer. Additional received bits are stored in the next
subsequent bit positions. After reception, RxAlign[2:0] is
automatically cleared. For example:
reserved
defines the number of bits of the last byte that shall be
transmitted. 000 indicates that all bits of the last byte will be
transmitted. TxLastBits[2:0] is automatically cleared after
transmission.
the LSB of the received bit is stored in bit position 0 and the
second received bit is stored in bit position 1
the LSB of the received bit is stored in bit position 1, the
second received bit is stored in bit position 2
the LSB of the received bit is stored in bit position 7, the
second received bit is stored in the next byte in bit position 0
D
5
4
R/W
3
0
ISO/IEC 14443 reader IC
2
TxLastBits[2:0]
MFRC531
© NXP B.V. 2010. All rights reserved.
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