MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 68

• Manufacturer Part Number: MFRC53101T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53101T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2224-5; 935269691112; MFRC531; MFRC53101TD

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
10.5.6.1 Page register
10.5.6.2 FIFOLevel register
10.5.6.3 TimerClock register
10.5.6 Page 5: FIFO, timer and IRQ pin configuration
Selects the page register; see
Defines the levels for FIFO underflow and overflow warning.
Table 108. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation
Table 109. FIFOLevel register bit descriptions
Selects the divider for the timer clock.
Table 110. TimerClock register (address: 2Ah) reset value: 0000 0111b, 07h bit allocation
Table 111. TimerClock register bit descriptions
Bit
Symbol
Access
Bit
7 to 6 00
5 to 0 WaterLevel[5:0] defines, the warning level of a FIFO buffer overflow or underflow:
Bit
Symbol
Access
Bit
7 to 6
5
4 to 0
Symbol
Symbol
00
TAutoRestart
TPreScaler[4:0] -
7
7
RW
00
R/W
00
6
Rev. 3.4 — 26 January 2010
Description
these values must not be changed
6
Value
-
1
0
HiAlert is set to logic 1, if the remaining FIFO buffer space is equal to
or less than the WaterLevel[5:0] bits in the FIFO buffer.
LoAlert is set to logic 1, if equal to or less than the WaterLevel[5:0] bits
in the FIFO buffer.
TAutoRestart
056634
Section 10.5.1.1 “Page register” on page
RW
Function
these values must not be changed
the timer automatically restarts its countdown from the
TReloadValue[7:0] instead of counting down to zero
the timer decrements to zero and register InterruptIrq
TimerIRq bit is set to logic 1
defines the timer clock frequency (f
TPreScaler[4:0] can be adjusted from 0 to 21. The following
formula is used to calculate the TimerClock frequency
(f
f
5
TimerClock
TimerClock
5
):
= 13.56 MHz / 2
4
4
WaterLevel[5:0]
3
3
TPreScaler
R/W
TPreScaler[4:0]
RW
2
ISO/IEC 14443 reader IC
2
[MHz]
TimerClock
MFRC531
© NXP B.V. 2010. All rights reserved.
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