PIC16F1828-I/SS Microchip Technology, PIC16F1828-I/SS Datasheet - Page 169

• Manufacturer Part Number: PIC16F1828-I/SS
• Description: IC PIC MCU 8BIT 14KB FLSH 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1828-I/SS

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.0
The module consists of a single SR latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR latch module includes the following features:
• Programmable input selection
• SR latch output is available externally
• Separate Q and Q outputs
• Firmware Set and Reset
The SR latch can be used in a variety of analog appli-
cations, including oscillator circuits, one-shot circuit,
hysteretic controllers, and analog timing applications.
18.1
The latch is a Set-Reset Latch that does not depend on
a clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by:
• Software control (SRPS and SRPR bits)
• Comparator C1 output (SYNCC1OUT)
• Comparator C2 output (SYNCC2OUT)
• SRI pin
• Programmable clock (SRCLK)
The SRPS and the SRPR bits of the SRCON0 register
may be used to Set or Reset the SR latch, respectively.
The latch is Reset-dominant. Therefore, if both Set and
Reset inputs are high, the latch will go to the Reset
state. Both the SRPS and SRPR bits are self resetting
which means that a single write to either of the bits is all
that is necessary to complete a latch Set or Reset oper-
ation.
The output from Comparator C1 or C2 can be used as
the Set or Reset inputs of the SR latch. The output of
either Comparator can be synchronized to the Timer1
clock
Module”
Gate Control”
An external source on the SRI pin can be used as the
Set or Reset inputs of the SR latch.
An internal clock source is available that can periodically
set or reset the SR latch. The SRCLK<2:0> bits in the
SRCON0 register are used to select the clock source
period. The SRSCKE and SRRCKE bits of the SRCON1
register enable the clock source to Set or Reset the SR
latch, respectively.
 2010 Microchip Technology Inc.
Note:
source.
SR LATCH
Latch Operation
and
Enabling both the Set and Reset inputs
from any one source at the same time
may result in indeterminate operation, as
the Reset dominance cannot be assured.
for more information.
Section 21.0 “Timer1 Module with
See
Section 19.0
“Comparator
Preliminary
18.2
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
latch outputs may be directly output to an I/O pin at the
same time.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
18.3
Upon any device Reset, the SR latch output is not ini-
tialized to a known state. The user’s firmware is
responsible for initializing the latch output before
enabling the output pins.
PIC16(L)F1824/1828
Latch Output
Effects of a Reset
DS41419B-page 169