PIC16F1828-I/SS Microchip Technology, PIC16F1828-I/SS Datasheet - Page 302

• Manufacturer Part Number: PIC16F1828-I/SS
• Description: IC PIC MCU 8BIT 14KB FLSH 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1828-I/SS

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 26-4:
TABLE 26-1:
 2010 Microchip Technology Inc.
APFCON0
BAUDCON
INLVLA
INLVLB
INLVLC
INTCON
PIE1
PIR1
RCSTA
SPBRGL
SPBRGH
TRISA
TRISB
TRISC
TXREG
TXSTA
Legend:
Note 1:
Note:
Reg. Empty Flag)
Name
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
(Transmit Shift
3)
(1)
2:
3:
(3)
(1)
BRG Output
(Shift Clock)
*
TRMT bit
TXIF bit
— = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
Page provides register information.
PIC16F/LF1828 only.
PIC16F/LF1824 only.
Unshaded cells apply to PIC16F/LF1824 only.
TX/CK
This timing diagram shows two consecutive transmissions.
EUSART Transmit Data Register
INLVLC7
RXDTSEL
TMR1GIE
TRISC7
TMR1GIF
ABDOVF
INLVLB7
pin
TRISB7
BRG15
CSRC
SPEN
BRG7
Bit 7
GIE
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
(1)
(1)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
1 T
CY
Transmit Shift Reg.
Word 1
SDOSEL
INLVLC6
TRISC6
Word 1
INLVLB6
TRISB6
BRG14
RCIDL
BRG6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
—
—
(1)
(2)
(1)
Start bit
Word 2
SSSEL
INLVLC5
INLVLA5
INLVLB5
TMR0IE
TRISA5
TRISB5
TRISC5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
—
(2)
1 T
CY
bit 0
INLVLC4
INLVLA4
INLVLB4
TRISC4
TRISA4
TRISB4
BRG12
Preliminary
CREN
SYNC
SCKP
BRG4
Bit 4
INTE
TXIE
TXIF
—
bit 1
Word 1
INLVLA3
INLVLC3
T1GSEL
TRISC3
SSP1IE
SSP1IF
ADDEN
TRISA3
SENDB
BRG16
BRG11
IOCIE
BRG3
Bit 3
—
—
PIC16(L)F1824/1828
TXCKSEL
INLVLA2
INLVLC2
TMR0IF
CCP1IE
CCP1IF
TRISC2
TRISA2
BRG10
BRGH
FERR
BRG2
Bit 2
—
—
—
bit 7/8
INLVLC1
INLVLA1
TMR2IE
TMR2IF
TRISC1
TRISA1
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
—
—
—
Word 2
Transmit Shift Reg.
Stop bit
INLVLA0
INLVLC0
TMR1IE
TMR1IF
TRISC0
ABDEN
TRISA0
IOCIF
RX9D
BRG0
BRG8
TX9D
Bit 0
Start bit
—
—
—
DS41419B-page 301
Word 2
Register on
Page
309*
309*
299*
122
308
128
133
139
307
126
132
132
306
93
94
97
bit 0