XRT75R03IVTR Exar Corporation, XRT75R03IVTR Datasheet - Page 76

• Manufacturer Part Number: XRT75R03IVTR
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRT75R03
REV. 1.0.8
B
IT
N
UMBER
3
2
FL Alarm Declared
Receive LOL Con-
dition Declared
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
N
AME
T
R/O
R/O
YPE
D
V
EFAULT
ALUE
0
0
73
FL (FIFO Limit) Alarm Declared:
This READ-ONLY bit-field indicates whether or not the Jit-
ter Attenuator block (within Channel_n) is currently declar-
ing the FIFO Limit Alarm.
The Jitter Attenuator block will declare the FIFO Limit
Alarm anytime the Jitter Attenuator FIFO comes within two
bit-periods of either overflowing or under-running.
Conversely, the Jitter Attenuator block will clear the FIFO
Limit Alarm anytime the Jitter Attenuator FIFO is NO
longer within two bit-periods of either overflowing or under-
running.
Typically, this Alarm will only be declared whenever there
is a very serious problem with timing or jitter in the system.
0 - Indicates that the Jitter Attenuator block (within
Channel_n) is NOT currently declaring the FIFO Limit
Alarm condition.
1 - Indicates that the Jitter Attenuator block (within
Channel_n) is currently declaring the FIFO Limit Alarm
condition.
N
Receive LOL (Loss of Lock) Condition Declared:
This READ-ONLY bit-field indicates whether or not the
Receive Section (within Channel_n) is currently declaring
the LOL (Loss of Lock) condition.
The Receive Section (of Channel_n) will declare the LOL
Condition, if any one of the following conditions are met.
•
•
0 - Indicates that the Receive Section of Channel_n is NOT
currently declaring the LOL Condition.
1 - Indicates that the Receive Section of Channel_n is cur-
rently declaring the LOL Condition.
OTE
If the frequency of the Recovered Clock signal differs
from that of the signal provided to the E3CLK input (for
E3
applications) or the STS-1CLK input (for STS-1
applications) by 0.5% (or 5000ppm) or more.
If the frequency of the Recovered Clock signal differs
from the line-rate clock signal (for Channel_n) that has
been generated by the SFM Clock Synthesizer PLL (for
SFM Mode Operation) by 0.5% (or 5000ppm) or more.
: This bit-field is only active if the Jitter Attenuator
applications),
(within Channel_n) has been enabled.
D
the
ESCRIPTION
DS3CLK
xr
xr
xr
xr
input
(for
DS3