XRT75R03IVTR Exar Corporation, XRT75R03IVTR Datasheet - Page 87

• Manufacturer Part Number: XRT75R03IVTR
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

xr
xr
xr
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
The XRT75R03 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. This feature is only available in Host mode. With the PRBSEN_n bit = “1”, the transmitter
will send out PRBS of 2
detector is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go
“Low” to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the
PRBSLS bit will be set to “1” and RNEG/LCV pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for one RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
Figure 25 shows the status of RNEG/LCV pin when the XRT75R03 is configured in PRBS mode.
N
The XRT75R03 offers three loopback modes for diagnostic purposes. In Hardware mode, the loopback modes
are selected via the RLB_n and LLB_n pins. In Host mode, the RLB_n and LLB_n bits n the Channel control
registers select the loopback modes.
F
B
9.0 DIAGNOSTIC FEATURES:
9.1
9.2
9.2.1
OTE
IGURE
IT
N
: In PRBS mode, the device is forced to operate in Single-Rail Mode.
UMBER
1
0
26. PRBS MODE
PRBS Generator and Detector:
LOOPBACKS:
ANALOG LOOPBACK:
RNEG/LCV
JA in Tx Path Ch_n
RClk
JA0 Ch_n
N
AME
23
SYNC LOSS
-1 in E3 rate or 2
PRBS SYNC
T
R/W
R/W
YPE
15
D
-1 in STS-1/DS3 rate. At the same time, the receiver PRBS
V
EFAULT
ALUE
0
0
Single Bit Error
84
Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator
(within Channel_n) to operate in either the Transmit or
Receive path, as described below.
0 - Configures the Jitter Attenuator (within Channel_n) to
operate in the Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to
operate in the Transmit Path.
Jitter Attenuator Configuration Select Input - Bit 0:
Please see the description for Bit 2 (JA1 Ch_n).
D
ESCRIPTION
XRT75R03
REV. 1.0.8