ATMEGA32A-MNR Atmel, ATMEGA32A-MNR Datasheet - Page 86

• Manufacturer Part Number: ATMEGA32A-MNR
• Description: IC MCU AVR 32K 16MHZ 44VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.9.2
14.9.3
8155C–AVR–02/11
TCNT0 – Timer/Counter Register
OCR0 – Output Compare Register
Table 14-5.
Note:
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 14-6.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
COM01
CS02
0
0
0
0
1
1
1
1
0
0
1
1
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
match is ignored, but the set or clear is done at TOP. See
80
COM00
CS01
for more details.
0
0
1
1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode
Clock Select Bit Description
0
1
0
1
R/W
R/W
7
0
7
0
CS00
Description
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on compare match when up-counting. Set OC0 on compare match
when downcounting.
Set OC0 on compare match when up-counting. Clear OC0 on compare match
when downcounting.
0
1
0
1
0
1
0
1
R/W
R/W
6
0
6
0
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge.
External clock source on T0 pin. Clock on rising edge.
I/O
I/O
I/O
I/O
I/O
R/W
R/W
5
0
5
0
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
R/W
4
0
4
0
TCNT0[7:0]
OCR0[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
“Phase Correct PWM Mode” on page
2
0
2
0
(1)
R/W
R/W
1
0
1
0
ATmega32A
R/W
R/W
0
0
0
0
TCNT0
OCR0
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