WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 137

• Manufacturer Part Number: WM8351GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8351GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
14.7.3
Each LDO Regulator is monitored for voltage accuracy and fault conditions. An undervoltage
condition is set if the voltage falls below 95% of the required level. The action taken in response to a
fault condition can be set independently for each LDO Regulator, as described in Table 85. The
LDOn_ERRACT fields configure the fault response to disable the respective regulator or to shut
down the entire system if desired. In addition, LDO Regulator fault conditions also generate a
second-level interrupt (see Section 24).
To prevent false alarms during short current surges, faults are only signalled if the fault condition
persists.
R201 (C9h)
for LDO1
R204 (CCh)
for LDO2
R207 (CFh)
for LDO3
R210 (D2h)
for LDO4
Note: n is a number between 1 and 4 that identifies the individual LDO regulator
Table 85 Fault Responses for LDO Regulators
The DC-DC Converters and the LDO Regulators have a first-level interrupt, UV_INT (see
Section 24). This comprises second-level interrupts from each of the DC-DC Converters and the
LDO Regulators.
Each LDO Regulator has a dedicated second-level interrupt which indicates an under-voltage
condition. These can be masked by setting the applicable mask bit as defined in Table 86.
R28 (1Ch)
Under Voltage
Interrupt Status
R36 (24h)
Under Voltage
Interrupt Mask
Table 86 LDO Regulator Interrupts
ADDRESS
ADDRESS
INTERRUPTS AND FAULT PROTECTION
15:14
as in
R28
BIT
BIT
11
10
9
8
LDOn_ERRACT
[1:0]
UV_LDO4_EINT
UV_LDO3_EINT
UV_LDO2_EINT
UV_LDO1_EINT
“IM_” + name of respective
bit in R28
LABEL
LABEL
DEFAULT
00
LDO4 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO3 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO2 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO1 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Mask bits for LDO regulator under-voltage
interrupts
Each of these bits masks the respective
bit in R28 when it is set to 1 (e.g.
UV_LDO1_EINT in R28 does not trigger a
UV_INT interrupt when
IM_UV_LDO1_EINT in R36 is set).
Action to take on fault (as well as
generating an interrupt):
00 = ignore
01 = shut down regulator
10 = shut down system
11 = reserved (shut down system)
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
WM8351
137