WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 249

• Manufacturer Part Number: WM8351GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8351GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
REGISTER
Register 44h ADC Divider
REGISTER
Register 46h ADC LR Rate
w
ADDRESS
ADC Divider
ADDRESS
R68 (44h)
R70 (46h)
ADC LR
Rate
BIT
BIT
10:0
11:8
7:4
2:0
11
3
ADCLRC_RATE[10:0] 000_0100_0000 Determines the number of bit clocks per LRC
ADCR_DAC_SVOL[3:0]
ADCL_DAC_SVOL[3:0]
ADC_CLKDIV[2:0]
ADCLRC_ENA
ADCCLK_POL
LABEL
LABEL
DEFAULT
DEFAULT
0000
0000
000
0
0
Controls left digital side tone volume from -
36dB to 0dB in 3dB steps.
Controls right digital side tone volume from -
36dB to 0dB in 3dB steps.
ADC Clock Polarity
0 = Normal
1 = Inverted
ADC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
Enables the LRC generation for the ADC
0 = disabled
1 = enabled
phase (when enabled)
00000000000 = invalid
...
00000000111 = invalid
00000001000 = 8 BCPS
…
11111111111 = 2047 BCPS
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
REFER TO
REFER TO
WM8351
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