WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 301

• Manufacturer Part Number: WM8351GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8351GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
REGISTER
Register CAh LDO1 Low Power
Register CBh LDO2 Control
w
REGISTER
ADDRESS
ADDRESS
R202 (CAh)
R203 (CBh)
LDO1 Low
Control
Power
LDO2
13:12
BIT
BIT
9:8
4:0
4:0
14
10
LDO1_HIB_MODE[1:0]
LDO2_VSEL[4:0]
LDO1_HIB_TRIG[1:0]
LDO2_OPFLT
LDO1_VIMG[4:0]
LDO2_SWI
LABEL
LABEL
DEFAULT
1_1011
1_0000
1_0000
1_0110
0
0
DEFAULT
1_1100
00
00
LDO2 Regulator mode
0 = LDO voltage regulator
1 = Current-limited switch (no voltage regulation,
LDO2_VSEL has no effect)
Reset by state machine. Default held in metal mask.
Enable discharge of LDO2 outputs when LDO2 is
disabled
0 = Enabled - Output to be discharged
1 = Disabled - Output is left floating
Note - if LDO Regulators 1, 2, 3 and 4 are all
disabled, then the outputs will all be discharged,
regardless of the LDOn_OPFLT bit.
LDO2 Regulator output voltage (when LDO2_SWI=0)
1 1111 = 3.3V
… (100mV steps)
1 0000 = 1.8V
0 1111 = 1.65V
… (50mV steps)
0 0000 = 0.9V
Reset by state machine. Default held in metal mask.
LDO1 Hibernate behaviour:
00 = Select voltage image settings
01 = disable output
10 = reserved
11 = reserved
Reset by state machine. Default held in metal
mask.
LDO1 Hibernate signal select
00 = Hibernate register bit
01 = L_PWR1
10 = L_PWR2
11 = L_PWR3
Reset by state machine. Default held in metal
mask.
LDO1 Regulator output image voltage
1 1111 = 3.3V
… (100mV steps)
1 0000 = 1.8V
0 1111 = 1.65V
… (50mV steps)
0 0000 = 0.9V
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
REFER TO
REFER TO
WM8351
301