WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 93
WM8351GEB/V
Manufacturer Part Number
WM8351GEB/V
Description
Audio CODECs Audio CODEC plus pwr management
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8351GEBV.pdf
(328 pages)
Specifications of WM8351GEB/V
Number Of Adc Inputs
2
Number Of Dac Outputs
2
Conversion Rate
48 KSPS
Interface Type
Serial (2-Wire, 3-Wire, 4-Wire)
Resolution
12 bit
Operating Supply Voltage
3.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA
Minimum Operating Temperature
- 25 C
Number Of Channels
2 ADC/2 DAC
Supply Current
260 uA
Thd Plus Noise
- 83 dB
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
8
No. Of Output Channels
6
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
95dB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 54 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=1)
13.10.2 AUDIO INTERFACE TDM MODE
The digital audio interface on WM8351 has the facility of tri-stating the ADCDAT pin to allow multiple
data sources to operate on the same bus. Time division multiplexing (TDM) is also supported,
allowing audio output data to be transferred simultaneously from two different sources.
TDM mode is enabled for the ADC and DAC by register bits AIFADC_TDM and AIFDAC_TDM
respectively. TDM slot selection for the WM8351 is set for the ADC and DAC by register bits
AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN respectively, as defined in Table 45. When not
actively transmitting data, the ADCDAT pin will be tristated in TDM mode, to allow other devices to
transmit data.
13.10.3 TDM DATA FORMATS
All selectable data formats support TDM. The allocation of time slots is controlled by register bits
AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN. Two possible slots (SLOT0 and SLOT1) are
available for the ADC and for the DAC.
Timing signals for the various interface formats in TDM mode are shown below for the ADC. Similar
slot allocation will exist for the DAC.
Left Justified Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles
from the start of SLOT0 to the start of SLOT1 is determined by the selected word length of the
interface of the WM8351.
Figure 55 Left Justified Mode with TDM
PD, March 2010, Rev 4.2
WM8351
93
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