ASD5020L640INT Arctic Silicon Devices, ASD5020L640INT Datasheet - Page 26

• Manufacturer Part Number: ASD5020L640INT
• Description: ADC (A/D Converters) Mul-Md 12bit/640MSPS 8-bit 1000 MSPS ADC
• Manufacturer: Arctic Silicon Devices

Specifications of ASD5020L640INT

• Number Of Converters: 1
• Number Of Adc Inputs: 2
• Conversion Rate: 640 MSPs
• Resolution: 12 bit
• Snr: 70 dB
• Voltage Reference: 1 V
• Supply Voltage (max): 2 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 490 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Input Voltage: 1.8 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preliminary Product Specification
Power Mode Control
The ASD5020 device has several modes for power management, from sleep modes with short start up time to full power
down with extremely low power dissipation. There are two sleep modes, both with the LVDS clocks (FCLK, LCLK)
running, such that the synchronization with the receiver is maintained. The first is a light sleep mode (sleep*_ch) with
short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down.
Setting sleep4_ch<n> = '1' sets channel <n> in a Quad Channel setup in sleep mode. Setting sleep2_ch<n> = '1' sets
channel <n> in a Dual Channel setup in sleep mode. Setting sleep1_ch1 = '1' sets the ADC channel in a Single Channel
setup in sleep mode. This is a light sleep mode with short start up time.
Setting sleep = '1', puts all channels to sleep, but keeps FCLK and LCLK running to maintain LVDS synchronization. The
start up time is the same as for complete power down. Power consumption is significantly lower than for setting all
channels to sleep by using the sleep*_ch register.
Setting pd = '1' completely powers down the chip, including the band-gap reference circuit. Start-up time from this mode
is significantly longer than from the sleep*_ch mode. The synchronization with the LVDS receiver is lost since LCLK and
FCLK outputs are put in high-Z mode.
Setting pdn_pin_cfg<1:0> = 'x1' configures the circuit to enter sleep channel mode (all channels off) when the PD pin is
set high. This is equal to setting all channels to sleep by using sleep*_ch. The channels can not be powered down
separately using the PD pin. Setting pdn_pin_cfg<1:0> = '10' configures the circuit to enter (deep) sleep mode when the
PD pin is set high (equal to setting sleep='1'). When pdn_pin_cfg <1:0>= '00', which is the default, the circuit enters the
power down mode when the PD pin is set high.
The lvds_pd_mode register configures whether the LVDS data output drivers are powered down or kept alive in sleep
and sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and sleep
channel modes. If lvds_pd_mode is set low (default), the LVDS output is put in high Z mode, and the driver is completely
powered down. If lvds_pd_mode is set high, the LVDS output is set to constant 0, and the driver is still on during sleep
and sleep channel modes.
ASD5020
sleep4_ch<4:1>
sleep2_ch<2:1>
sleep1_ch1
sleep
pd
pd_pin_cfg<1:0>
lvds_pd_mode
Name
Channel-specific sleep mode for a
Quad Channel setup.
Channel-specific sleep mode for a
Dual Channel setup.
Channel-specific sleep mode for a
Single Channel setup.
Go to sleep-mode.
Go to power-down.
Configures the PD pin function.
Controls LVDS power down mode
Description
PD pin configured
for power-down
rev 2.0, 2010.11.08
High z-mode
Default
Inactive
Inactive
Inactive
Inactive
Inactive
Page 26 of 34
mode
D15 D14D13D12D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X X
X X X X
High Speed Mode
X
Address
0x0F
0x52
Hex