AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 124

• Manufacturer Part Number: AGLP060V5-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V5-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4- 4
Revision
Revision 4 (Jul 2008)
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.3
Revision 3 (Jun 2008)
DC and Switching
Characteristics
Advance v0.2
Packaging v1.3
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
Tables have been updated to reflect default values in the software. The default
I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V
I/O set.
Table note 3 was updated in
to add the sentence, "V
bank." References to table notes 5, 6, 7, and 8 were added. Reference to table
note 3 was removed from V
Table 2-4 • Overshoot and Undershoot Limits 1
measured on quiet I/Os" from the title. Table note 2 was revised to remove
"estimated SSO density over cycles." Table note 3 was deleted.
The table note for
IGLOO PLUS Flash*Freeze Mode*
not include I/O static contribution.
The table note for
IGLOO PLUS Sleep Mode*
statement that values do not include I/O static contribution.
The table note for
IGLOO PLUS Shutdown Mode
do not include I/O static contribution.
Note 2 of
Flash*Freeze Mode 1
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings
I/O Software Settings1
were updated to reflect that power was measured on V
added to
Software
Table 2-16 • Different Components Contributing to the Static Power Consumption
in IGLOO PLUS Devices
the Static Power Consumption in IGLOO PLUS Devices
the definition for P
subtitles were added for
Static Power Consumption in IGLOO PLUS
Components Contributing to Dynamic Power Consumption in IGLOO PLUS
Devices, and
Consumption in IGLOO PLUS
The
Table 2-32 • Schmitt Trigger Input Hysteresis
The
The
"Total Static Power Consumption—PSTAT" section
"281-Pin CSP"
"281-Pin CSP"
and
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O
Settings.
Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default
Table 2-18 • Different Components Contributing to the Static Power
Table 2-10 • Quiescent Supply Current (IDD) Characteristics,
Table 2-11 • Quiescent Supply Current (IDD) Characteristics,
DC5
Table 2-9 • Quiescent Supply Current (IDD) Characteristics,
package drawing is new.
table for the AGLP125 device is new.
was updated to include V
from bank static power to bank quiescent power. Table
were updated to remove static power. The table notes
CCI
Table 2-16 • Different Components Contributing to the
and
PUMP
Table 2-2 • Recommended Operating Conditions1,2
should be at the same voltage within a given I/O
was updated to remove V
Table 2-18 • Different Components Contributing to
Devices.
was updated to remove the statement that values
R ev isio n 1 1
Operation and placed next to V
to remove the sentence stating that values do
Changes
is new.
CCPLL
Devices,
was revised to remove "as
. Table note 4 was deleted.
was revised.
were updated to change
JTAG
CCI
Table 2-17 • Different
. Table note 2 was
and V
CC
.
CCI
and the
2-9,
Page
2-11,
2-12
2-12
2-26
3-13
3-13
N/A
N/A
2-2
2-3
2-7
2-7
2-8
2-8
2-9