AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 26

• Manufacturer Part Number: AGLP060V5-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V5-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO PLUS DC and Switching Characteristics
Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
2- 12
Parameter
PDC1
PDC2
PDC3
PDC4
PDC5
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator
or the SmartPower tool in Actel Libero IDE software.
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
Global Clock Contribution—P
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
Bank quiescent power (VCCI-dependent)
•
•
•
•
•
•
•
•
P
P
P
P
TOTAL
STAT
DYN
CLOCK
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-20 on page
design.
P
P
N
N
Table 2-19 on page
N
Table 2-19 on page
= P
= (P
STAT
DYN
BANKS
SPINE
ROW
= P
= (P
2-14.
2-14.
CLOCK
DC1
STAT
is the total dynamic power consumption.
is the total static power consumption.
AC1
is the number of VersaTile rows used in the design—guidelines are provided in
is the number of global spines used in the user design—guidelines are provided in
is the number of I/O banks powered in the design.
or P
+ P
+ P
+ N
DC2
DYN
S-CELL
Definition
SPINE
2-14. The calculation should be repeated for each clock domain defined in the
or P
*P
2-14.
2-14.
+ P
DC3
AC2
C-CELL
) + N
TOTAL
CLOCK
+ N
ROW
BANKS
+ P
STAT
*P
R ev i sio n 1 1
NET
AC3
* P
DYN
+ P
DC5
+ N
INPUTS
S-CELL
AGLP125
+ P
* P
Device-Specific Static Power (mW)
OUTPUTS
AC4
See
See
See
) * F
See
CLK
Table 2-12 on page 2-8
Table 2-11 on page 2-8
Table 2-12 on page 2-8
Table 2-9 on page 2-7
+ P
AGLP060
MEMORY
0.90
1
+ P
PLL
Table 2-19 on
Table 2-20 on
AGLP030