AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 19

• Manufacturer Part Number: AGLP060V5-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V5-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Deactivation trip point:
Activation trip point:
V a = 0.85 V ± 0.2 V
V d = 0.75 V ± 0.2 V
VCC = 1.575 V
VCC = 1.14 V
V
CC
Region 1: I/O Buffers are OFF
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
Deactivation trip point:
Activation trip point:
V
V
a
d
= 0.9 V ± 0.15 V
= 0.8 V ± 0.15 V
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
buffers do not meet VOH / VOL levels.
meet VIH / VIL levels, and output
same reason, input buffers do not
below specification. For the
but slower because VCCI is
(except differential
(except differential inputs)
I/Os are functional
I/Os are functional
R ev i si o n 1 1
buffers are ON.
buffers are ON.
Region 4: I/O
Region 4: I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
Min VCCI datasheet specification
voltage at a selected I/O
2.3 V, or 3.0 V
speed, VIH / VIL , VOH / VOL , etc.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
IGLOO PLUS Low Power Flash FPGAs
VCCI
2 -5