AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 76

• Manufacturer Part Number: AGLP060V5-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V5-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO PLUS DC and Switching Characteristics
Table 2-91 • IGLOO PLUS CCC/PLL Specification
2- 62
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
VCO Output Peak-to-Peak Period Jitter F
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions.For specific junction
4. The AGLP030 device does not support PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
7. Measurements are done with LVTTL 3.3 V, 8 mA, I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V,
8. SSO are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ±200 ps of each
temperature and voltage supply levels, refer to
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider
settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output
divider settings.
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
other. Switching I/Os are placed outside of the PLL bank. Refer to the "ProASIC3/E SSO and Pin Placement Guidelines"
chapter of the
0.75 MHz to 50 MHz
50 MHz to 160 MHz
J
= 25°C, V
For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage
5
CC
ProASIC3 FPGA Fabric User’s Guide.
= 1.2 V
1, 2
3,4
CCC_OUT
IN_CCC
1, 2
1, 2
OUT_CCC
Table 2-6 on page 2-6
1, 2
6
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
R ev i sio n 1 1
Table 2-6 on page 2-6
and
SSO ≤ 2
0.50%
2.50%
0.025
Min.
0.75
Maximum Peak-to-Peak Period Jitter
48.5
Table 2-7 on page 2-7
2.3
1.5
and
Table 2-7 on page 2-7
SSO ≤ 4
1.20%
5.00%
Typ.
580
5.7
for derating values.
SSO ≤ 8
2.00%
7.00%
20.86
20.86
Max.
160
160
300
51.5
6.0
60
32
4
3
for deratings.
SSO ≤ 16
15.00%
3.00%
Units
MHz
MHz
MHz
ms
µs
ns
ns
6,7,8
ps
%
ns
ns
ns