AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 69

• Manufacturer Part Number: AGLP060V5-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V5-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-20 • Timing Model and Waveforms
Table 2-82 • Register Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLK
Data
EN
Out
PRE
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
CLR
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
1.5 V DC Core Voltage
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
PRE2Q
50%
50%
J
50%
t
= 70°C, Worst-Case VCC = 1.425 V
WPRE
50%
Description
50%
50%
t
t
RECPRE
R ev i si o n 1 1
WCLR
50%
t
50%
50%
CLR2Q
50%
t
RECCLR
Table 2-6 on page 2-6
IGLOO PLUS Low Power Flash FPGAs
50%
t
CKMPWH
t
50%
REMPRE
for derating values.
t
CKMPWL
50%
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
Std.
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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