AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 29

• Manufacturer Part Number: AGLP060V5-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V5-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User I/O Characteristics
Figure 2-3 • Timing Model
Input LVCMOS 2.5 V
LVCMOS 1.5 V
t
PY
= 0.85 ns
Clock
Input LVTTL
Timing Model
Operating Conditions: STD Speed, Commercial Temperature Range (T
V
CC
= 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
t
PY
(Non-Registered)
(Registered)
= 1.06 ns
I/O Module
I/O Module
t
t
PY
t
ICLKQ
ISUD
= 1.15 ns
= 0.18 ns
= 0.63 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.84 ns
= 0.80 ns
Q
Combinational Cell
Combinational Cell
t
PD
Combinational Cell
t
PD
Clock
Input LVTTL
t
PY
= 1.98 ns
t
= 1.40 ns
PD
= 0.85 ns
= 0.87 ns
Combinational Cell
Combinational Cell
Y
Y
t
PD
t
PD
R ev i si o n 1 1
Y
= 1.24 ns
= 0.86 ns
Register Cell
Combinational Cell
t
t
CLKQ
SUD
D
t
PD
Y
Y
= 0.84 ns
(Non-Registered)
= 0.80 ns
= 0.89 ns
t
I/O Module
Q
DP
t
Clock
Input LVTTL
PY
(Non-Registered)
(Non-Registered)
= 1.62 ns
t
t
DP
I/O Module
I/O Module
DP
= 0.85 ns
Y
= 2.07 ns
= 1.70 ns
(Non-Registered)
I/O Module
t
DP
LVTTL Output drive strength = 12 mA
= 1.62 ns
t
t
D
OCLKQ
OSUD
(Registered)
I/O Module
IGLOO PLUS Low Power Flash FPGAs
High slew rate
LVTTL Output drive strength = 8 mA
LVCMOS 1.5 V Output drive strength = 4 mA
Q
= 0.18 ns
= 0.89 ns
t
DP
High slew rate
= 1.62 ns
LVCMOS 2.5 V Output Drive
Strength = 12 mA High Slew Rate
J
= 70°C), Worst-Case
High slew rate
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
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