LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 123
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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February 2010
Introduction
This user’s guide describes the clock resources available in the LatticeXP2™ device architecture. Details are pro-
vided for primary clocks, secondary clocks and edge clocks as well as clock elements such as PLLs, clock dividers
and more.
The number of PLLs and DDR-DLLs for each device is listed in Table 9-1.
Table 9-1. Number of PLLs and DDR-DLLs
Clock/Control Distribution Network
LatticeXP2 devices provide global clock distribution in the form of eight quadrant-based primary clocks and flexible
secondary clocks. Two edge clocks are also provided on every edge of the device. Other clock sources include
clock input pins, internal nodes, PLLs, and clock dividers.
LatticeXP2 Top Level View
Figure 9-1 provides a view of the primary clocking structure of the LatticeXP2-40 device.
Figure 9-1. LatticeXP2 Clocking Structure (LFXP2-40)
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
Number of GPLLs
Number of DDR-DLLs DDL for DDR applications
Parameter
General purpose PLL
ECLK2
ECLK1
ECLK2
Description
ECLK1
sysIO Bank 0
sysIO Bank 5
QUADRANT TL
QUADRANT BL
Primary Clocks
9-1
XP2-5
QUADRANT TR
QUADRANT BR
2
2
LatticeXP2 sysCLOCK PLL
sysIO Bank 1
sysIO Bank 4
Design and Usage Guide
XP2-8
2
2
XP2-17
4
2
XP2-30
4
2
Technical Note TN1126
XP2-40
4
2
tn1126_01.1
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