LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 173
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LatticeXP2 Memory Usage Guide
First In First Out (FIFO, FIFO_DC) – EBR Based
FIFOs are not supported in certain devices such as the LatticeECP/EC, LatticeECP2/M, LatticeXP and MachXO.
The hardware has Embedded Block RAM (EBR) which can be configured in Single Port (RAM_DQ), Pseudo-Dual
Port (RAM_DP) and True Dual Port (RAM_DP_TRUE) RAMs. The FIFOs in these devices can be emulated FIFOs
that are built around these RAMs. The IPexpress point tool in the ispLEVER design software allows users to build a
FIFO and FIFO_DC around Pseudo Dual Port RAM (or DP_RAM).
Each of these FIFOs can be configured with (pipelined) and without (non-pipelined) output registers. In the pipe-
lined mode users have an extra option to enable the output registers by the RdEn signal. We will discuss the oper-
ation in the following sections.
Let us take a look at the operation of these FIFOs.
First In First Out (FIFO) Memory
The FIFO, or the single clock FIFO, is an emulated FIFO. The address logic and the flag logic is implemented in the
FPGA fabric around the RAM.
The ports available on the FIFO are:
• Reset
• Clock
• WrEn
• RdEn
• Data
• Q
• Full Flag
• Almost Full Flag
• Empty Flag
• Almost Empty Flag
Let us first discuss the non-pipelined or the FIFO without output registers. Figure 10-21 shows the operation of the
FIFO when it is empty and the data starts to get written into it.
10-23
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