LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 125
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 9-2 describes the structure of the secondary clocks and edge clocks.
Figure 9-2. LatticeXP2 Secondary Clocks and Edge Clocks (LFXP2-40)
Primary Clock Note
The CLKOP must be used as the feedback source to optimize PLL performance.
Most designers use PLLs for clock tree injection removal mode and the CLKOP should be assigned to a primary
clock. This is done automatically by the software unless otherwise specified by the user.
CLKOP can route only to CLK0 to CLK5, while CLKOS/CLKOK can route to all primary clocks (CLK0 TO CLK7).
When CLK6 or CLK7 is used as a primary clock and there is only one clock input to the DCS, the DCS is assigned
as a buffer mode by the software. Please see the DCS section of this document for detailed information.
Specifying Clocks in the Design Tools
If desired, designers can specify the clock resources, primary, secondary or edge to be used to distribute a given
clock source. Figure 9-3 illustrates how this can be done in the Pre-map Preference editor. Alternatively, the prefer-
ence file can be used, as discussed in Appendix C.
Primary-Pure and Primary-DCS
Primary Clock Net can be assigned to either Primary-Pure (CLK0 to CLK5) or Primary-DCS (CLK6 and CLK7).
Global Primary Clock and Quadrant Primary Clock
Global Primary Clock
If a primary clock is not assigned as a quadrant clock, the software assumes it is a global clock.
There are six Global Primary/Pure clocks and two Global Primary/DCS clocks available.
ECLK1
ECLK1
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
sysIO Bank 0
sysIO Bank 5
Region 2
Region 3
Region 4
Region 1
DSP Row
DSP Row
EBR Row
9-3
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region 5
Region 6
Region 7
Region 8
sysIO Bank 1
sysIO Bank 4
ECLK2
ECLK2
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
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