LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 187
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based
PFU-based Distributed Dual Port RAM is also created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create a larger Distributed Memory sizes.
Figure 10-42. Distributed Dual Port RAM Module Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is
generated by utilizing the resources available in the PFU.
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn), are not available in the hardware prim-
itive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions for memory are as per Table 10-15. The table lists the corresponding ports
for the module generated by IPexpress and for the primitive.
Table 10-15. PFU-based Distributed Dual-Port RAM Port Definitions
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress config-
uration.
Generated Module
Port Name in
RdAddress
RdClockEn
WrClockEn
WrAddress
RdClock
WrClock
Data
WE
Q
RdClockEn
WrClockEn
WrAddress
RdAddress
Port Name in the EBR
RdClock
WrClock
Block Primitive
Reset
Data
WE
WAD[3:0]
RDO[1:0]
RAD[3:0]
DI[1:0]
WCK
WRE
—
—
—
Distributed Dual Port
10-37
PFU based
Memory
Read Clock Enable
Write Clock Enable
Read Address
Write Address
Write Enable
Description
Read Clock
Write Clock
Data Input
Data Out
LatticeXP2 Memory Usage Guide
Q
Rising Clock Edge
Rising Clock Edge
Active State
Active High
Active High
Active High
—
—
—
—
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