LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 278

• Manufacturer Part Number: LFXP2-5E-5TN144I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5TN144I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 100
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
parameter REG_SIGNEDB_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDB_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDB_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB1_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB1_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB1_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB1_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB1_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB1_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB3_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB3_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB3_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB3_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB3_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB3_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter GSR = “ Enabled, Disabled “;
MULT18X18MACB
input A17,A16,A15,A14,A13,A12,A11,A10,A9;
input A8,A7,A6,A5,A4,A3,A2,A1,A0;
input B17,B16,B15,B14,B13,B12,B11,B10,B9;
input B8,B7,B6,B5,B4,B3,B2,B1,B0;
input ADDNSUB, SIGNEDA, SIGNEDB,ACCUMSLOAD;
input SOURCEA, SOURCEB;
input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3;
input LD51, LD50, LD49, LD48, LD47, LD46, LD45, LD44, LD43, LD42, LD41, LD40
input LD39, LD38, LD37, LD36, LD35, LD34, LD33, LD32, LD31, LD30
input LD29, LD28, LD27, LD26, LD25, LD24, LD23, LD22, LD21, LD20
input LD19, LD18, LD17, LD16, LD15, LD14, LD13, LD12, LD11, LD10
input LD9, LD8, LD7, LD6, LD5, LD4, LD3, LD2, LD1, LD0;
input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9;
input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0;
input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9;
input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0;
output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9;
output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0;
output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9;
output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0;
output
ACCUM51,ACCUM50,ACCUM49,ACCUM48,ACCUM47,ACCUM46,ACCUM45,ACCUM44,ACCUM43,ACCUM42,ACCUM41,ACCUM40,AC
CUM39,ACCUM38,ACCUM37,ACCUM36,ACCUM35,ACCUM34,ACCUM33,ACCUM32,ACCUM31,ACCUM30,ACCUM29,ACCUM28,ACCU
M27,ACCUM26,ACCUM25,ACCUM24,ACCUM23,ACCUM22,ACCUM21,ACCUM20,ACCUM19,ACCUM18,ACCUM17,ACCUM16,ACCUM1
5,ACCUM14,ACCUM13,ACCUM12,ACCUM11,ACCUM10,ACCUM9,ACCUM8,ACCUM7,ACCUM6,ACCUM5,ACCUM4,ACCUM3,ACCUM2,
ACCUM1,ACCUM0,OVERFLOW;
parameter REG_INPUTA_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTA_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTA_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTB_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTB_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTB_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_PIPELINE_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_OUTPUT_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_OUTPUT_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_OUTPUT_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDA_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_1_CE = “ CE0, CE1, CE2, CE3 “;
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