A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 153

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Advance v0.5
(continued)
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
The "Introduction" of the "Introduction" section was updated.
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 • VCCI Voltages and Compatible Standards
Table 2-35 • ProASIC3E I/O Features was updated.
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
The notes in Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3E Devices were updated.
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
A footnote was added to Table 2-37 • Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength
and high slew selected).
Table 2-48 • ProASIC3E I/O Attributes vs. I/O Standard Applications
Table 2-55 • ProASIC3 I/O Standards—SLEW and Output Drive (OUT_DRIVE)
Settings
The "x" was updated in the "Pin Descriptions" section.
The "V
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected.
EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options.
CC
Core Supply Voltage" pin description was updated.
R e v i s i o n 9
Changes
ProASIC3E Flash Family FPGAs
Page
2-25
2-28
2-21
2-25
2-28
2-81
2-50
2-24
2-25
2-27
2-24
2-25
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2-27
2-29
2-54
2-32
2-35
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2-64
2-41
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2-50
2-50
N/A
N/A
2-8
4 -5