A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 25

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User I/O Characteristics
Figure 2-2 • Timing Model
Clock
Input LVTTL/LVCMOS
LVPECL
M-LVDS
BLVDS,
LVDS,
Timing Model
t
Operating Conditions: –2 Speed, Commercial Temperature Range (T
V
PY
CC
= 0.90 ns
= 1.425 V
t
PY
(Non-Registered)
(Registered)
I/O Module
t
I/O Module
PY
= 1.22 ns
t
t
ICLKQ
ISUD
= 1.36 ns
= 0.26 ns
= 0.24 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.43 ns
= 0.55 ns
Combinational Cell
Q
Clock
Combinational Cell
Input LVTTL/LVCMOS
t
PD
t
Combinational Cell
PD
= 0.87 ns
= 0.56 ns
t
Combinational Cell
Combinational Cell
PY
t
PD
t
= 0.90 ns
PD
= 0.47 ns
R e v i s i o n 9
t
PD
= 0.51 ns
Y
= 0.47 ns
Y
Y
Y
Y
Combinational Cell
Input LVTTL/LVCMOS
t
Register Cell
Clock
PD
t
t
CLKQ
SUD
(Non-Registered)
D
(Non-Registered)
= 0.49 ns
(Non-Registered)
I/O Module
t
I/O Module
t
DP
= 0.43 ns
I/O Module
t
DP
DP
= 0.55 ns
t
PY
Q
= 3.30 ns
= 2.39 ns
= 2.74 ns
= 0.90 ns
Y
(Non-Registered)
J
t
ProASIC3E Flash Family FPGAs
= 70°C), Worst-Case
DP
I/O Module
LVTTL/LVCMOS
Output drive strength = 24 mA
High slew rate
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
D
= 1.36 ns
t
t
CLKQ
SUD
(Registered)
I/O Module
= 0.31 ns
Q
= 0.59 ns
t
DP
= 1.53 ns
LVPECL
GTL+ 3.3V
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