A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 51

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-48 • Minimum and Maximum DC Input and Output Levels
Figure 2-11 • AC Loading
Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-50 • 3.3 V GTL
3.3 V GTL
Drive
Strength
25 mA
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
Input Low (V)
VREF – 0.05
*
Speed
Grade
Std.
–1
–2
Note:
Measuring point = V
3
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Voltage-Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The V
Min.
–0.3
Timing Characteristics
V
t
DOUT
0.60
0.51
0.45
VREF – 0.05 VREF + 0.05
VIL
Input High (V)
trip
VREF + 0.05
Max.
. See
2.08
1.77
1.55
t
V
DP
Table 2-15 on page 2-19
0.04
0.04
0.03
t
DIN
Min.
V
2.93
2.50
2.19
Measuring
t
VIH
Point* (V)
PY
Test Point
J
0.8
= 70°C, Worst-Case VCC = 1.425 V,
Max.
3.6
t
V
0.43
0.36
0.32
EOUT
GTL
for a complete table of trip points.
R e v i s i o n 9
Max.
VOL
0.4
VREF (typ.) (V)
V
V
2.04
1.73
1.52
t
TT
ZL
CCI
25
10 pF
0.8
pin should be connected to 3.3 V.
VOH
Min.
V
2.08
1.77
1.55
–
t
ZH
Table 2-6 on page 2-5
mA mA
I
25 25
OL
t
LZ
I
VTT (typ.) (V)
OH
t
HZ
1.2
Max.
mA
I
181
OSL
ProASIC3E Flash Family FPGAs
1
4.27
3.63
3.19
t
ZLS
for derating values.
Max.
I
mA
268
OSH
t
4.31
3.67
3.22
ZHS
C
1
LOAD
10
µA
10
I
(pF)
Units
IL
ns
ns
ns
2
µA
2- 39
I
10
IH
2