A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 21

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A3PE1500-PQG208

Manufacturer Part Number
A3PE1500-PQG208
Description
FPGA - Field Programmable Gate Array 1500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3PE1500-PQG208

Processor Series
A3PE1500
Core
IP Core
Maximum Operating Frequency
231 MHz
Number Of Programmable I/os
147
Data Ram Size
276480
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1.5 M
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3PE1500-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3PE1500-PQG208
Manufacturer:
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Part Number:
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Manufacturer:
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Part Number:
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Manufacturer:
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Quantity:
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Table 2-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices
Parameter
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Note:
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or
SmartPower in Actel Libero
Power Consumption of Various Internal Resources
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile used as a sequential
module
First contribution of a VersaTile used as a sequential
module
Second contribution of a VersaTile used as a sequential
module
Contribution of a VersaTile used as a combinatorial
module
Average contribution of a routing net
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read
operation
Average contribution of a RAM block during a write
operation
Static PLL contribution
Dynamic contribution for PLL
®
Integrated Design Environment (IDE).
Definition
R e v i s i o n 9
Device-Specific Dynamic Contributions
A3PE600
12.77
1.85
See
See
Table 2-8 on page
Table 2-9 on page 2-8
A3PE1500
ProASIC3E Flash Family FPGAs
(µW/MHz)
2.55 mW
16.21
25.00
30.00
3.06
0.88
0.12
0.07
0.29
0.29
0.70
2.60
2-6.
A3PE3000
19.7
4.16
2 -9

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