MC13892AJVL Freescale Semiconductor, MC13892AJVL Datasheet - Page 44

• Manufacturer Part Number: MC13892AJVL
• Description: IC PMU I.MX51/37/35/27 186MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC13892AJVL

• Applications: Battery Management, Display (LED Drivers), Handheld/Mobile Devices, Power Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 186-LFBGA
• Mounting Style: SMD/SMT
• Duty Cycle (max): 55 %
• Input Voltage: - 0.3 V to + 20 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Output Current: 30 mA
• Output Voltage: 3.3 V
• Topology: Boost
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Package Type: BGA
• Case Length: 12mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
44
Table 11. SPI Interface Logic IO Specifications
13892
Table 10. SPI Interface Timing Specifications
Notes
34.
T
T
T
T
T
T
T
T
T
T
T
T
Input Low CS, MOSI, CLK
Input High CS, MOSI, CLK
Output Low MISO, INT
Output High MISO, INT
SPIVCC Operating Range
MISO Rise and Fall Time
SELSU
SELHLD
SELLOW
CLKPER
CLKHIGH
CLKLOW
WRTSU
WRTHLD
RDSU
RDHLD
RDEN
RDDIS
Parameter
This table reflects a maximum SPI clock frequency of 26 MHz
Parameter
Time CS has to be high before the first rising edge of CLK
Time CS has to remain high after the last falling edge of CLK
Time CS has to remain low between two transfers
Clock period of CLK
Part of the clock period where CLK has to remain high
Part of the clock period where CLK has to remain low
Time MOSI has to be stable before the next rising edge of CLK
Time MOSI has to remain stable after the rising edge of CLK
Time MISO will be stable before the next rising edge of CLK
Time MISO will remain stable after the falling edge of CLK
Time MISO needs to become active after the rising edge of CS
Time MISO needs to become inactive after the falling edge of CS
Output sink 100 μA
Output source 100 μA
CL = 50 pF, SPIVCC = 1.8 V
SPIDRV[1:0] = 00 (default)
SPIDRV[1:0] = 01
SPIDRV[1:0] = 10
SPIDRV[1:0] = 11
Condition
Description
0.7*SPIVCC
SPIVCC-0.2
1.75
Min
0
0
-
-
-
-
High Z
Typ
6.0
11
22
-
-
-
-
-
Analog Integrated Circuit Device Data
SPIVCC+0.3
0.3*SPIVCC
SPIVCC
Max
0.2
3.1
Freescale Semiconductor
-
-
-
-
T min (ns)
4.0
4.0
4.0
4.0
4.0
4.0
Units
15
15
15
38
15
15
ns
ns
ns
ns
V
V
V
V
V