KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 15

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The SDO pin requires an external 4.7kΩ pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should be
connected to an open-drain driver with a drive strength of
less than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 21. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output returns
to normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range
condition the OR pin will stay high, and it will not be possible
to detect the end of the calibration cycle.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 500MSPS
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
User Initiated Reset
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength of less than
0.5mA is recommended, RESETN has an internal high
impedance pull-up to OVDD. As is the case during power-on
reset, the SDO, RESETN and DNC pins must be in the
proper state for the calibration to successfully execute.
The performance of the KAD5512P-50 changes with
variations in temperature, supply voltage or sample rate. The
extent of these changes may necessitate recalibration,
depending on system performance requirements. Best
performance will be achieved by recalibrating the ADC under
the environmental conditions at which it will operate.
CLKOUTP
RESETN
CLKN
CLKP
ORP
FIGURE 21. CALIBRATION TIMING
CALIBRATION
BEGINS
15
CALIBRATION
CALIBRATION
COMPLETE
TIME
KAD5512P-50
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.5dBFS and SFDR
change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less than
80MSPS will typically result in an SNR change of less than
0.5dBFS and an SFDR change of less than 3dBc.
Figures 22 and 23 show the effect of temperature on SNR
and SFDR performance with calibration performed at -40°C,
+25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single calibration at
-40°C, +25°C and +85°C. Best performance is typically
achieved by a user-initiated calibration at the operating
conditions, as stated earlier. However, it can be seen that
performance drift with temperature is not a very strong
function of the temperature at which the calibration is
performed..
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 1.45V, centered at the VCM voltage
of 0.535V as shown in Figure 24.
FIGURE 22. SNR PERFORMANCE vs TEMPERATURE AFTER
FIGURE 23. SFDR PERFORMANCE vs TEMPERATURE AFTER
-1
-2
-3
-4
-10
-15
3
2
1
0
-40
15
10
-5
5
0
-40
+25°C CALIBRATION
+25°C CALIBRATION
-15
-15
CAL DONE AT
CAL DONE AT
-40°C
CAL DONE AT
TEMPERATURE (°C)
CAL DONE AT
TEMPERATURE (°C)
-40°C
10
+85°C
+85°C
10
35
35
CAL DONE AT
+25°C
CAL DONE AT
+25°C
60
60
October 9, 2009
FN6805.3
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