KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 29

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Revision History
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
12/05/08 FN6805.0 Converted to intersil template. Assigned file number FN6805. Rev 0 - first release (as preliminary datasheet) with new file number.
12/23/08 FN6805.1 P1; revised Key Specs
7/30/08
5/08/09
8/25/09
DATE
REVISION
FN6805.2 1) Updated SINAD typ spec at 364MHz
Rev 1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Initial Release of Production Datasheet
p2; added Part Marking column to Order Info
P3; moved Thermal Resistance to Thermal Info table and added Theta JA note 3 per packaging
P3-6; revisions throughout spec tables. Added notes 6 and 7 to Switching Specs.
P5; revised Figs 1 and 2 (D[11:0])
P7; revised function for Pin 22 OUTMODE, Pin 23 NAPSLP and Pin 70 OUTFMT
P9-11; Perf. curves revised throughout
P13; User Initiated Reset - revised 2nd sentence of 1st paragraph
P18; Serial Peripheral Interface- 1st paragraph; revised 2nd and 4th sentences. 4th paragraph; revised 2nd sentence
P19; Address 0x24: Gain_Fine; added 2 sentences to end of 1st paragraph.
Revised Table 8
P20; removed Figure (PHASE SLIP: CLK÷1 MODE, fCLOCK = 500MHz)
P23; Revised Fig 43
P24; Table 17; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil standards
2) Added nap mode, sleep mode wake up times to spec table
3) Added CSB,SCLK Setup time specs for nap,sleep modes to spec table
4) Changed SPI setup spec wording in spec table
5) Change to pin description table for clarification
6) Added thermal pad note
7) Updated fig 22 and fig 23 and description in text.
8) Update multiple device usage note on at “SPI Physical Interface” on page 20
9) Added ‘Reserved’ to SPI memory map at address 25H
10) Added section on “ADC Evaluation Platform” on page 27
11) Updated table “DIFFERENTIAL SKEW ADJUSTMENT” on page 22.
Intersil Standards - Added Pb-free bullet in features, added Pb-free reflow link in Thermal Information, Placed caution statement
before Note to follow template standard, Added over-temp note reference and note to electrical spec tables, updated all cross
references.
12)Updated TOC and changed on page 20 2nd paragraph of SPI Physical Interface “SDIO” to “SDO”
13) Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs.
14) Updated SPI timing diagrams, Figures 34,35
15) Updated wakeup time description in “Nap/Sleep” on page 17.
16) Updated sleep mode power spec
17) Changed label in fig 44
18) Updated cal paragraph in user initiated reset section per DC.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
For information regarding Intersil Corporation and its products, see www.intersil.com
29
KAD5512P-50
CHANGE
October 9, 2009
FN6805.3