KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 25

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Memory Map
ADDR
76-BF
26-5F
60-6F
(Hex)
03-07
11-1F
00
01
02
08
09
10
20
21
22
23
24
25
70
71
72
73
74
75
device_index_A
output_mode_A
output_mode_B
PARAMETER
offset_coarse
gain_medium
config_status
chip_version
gain_coarse
port_config
phase_slip
offset_fine
burst_end
skew_diff
gain_fine
reserved
reserved
reserved
reserved
reserved
reserved
chip_id
NAME
modes
25
(MSB)
Active
BIT 7
SDO
other codes = reserved
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
1 = slow
0 = fast
clock_divide
Range
Result
BIT 6
XOR
First
DLL
LSB
Reserved
Reserved
Reset
BIT 5
Soft
TABLE 17. SPI MEMORY MAP
Reserved
KAD5512P-50
Burst end address [7:0]
Reserved
BIT 4
Differential Skew
Chip Version #
Coarse Offset
Medium Gain
Fine Offset
Fine Gain
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Chip ID #
BIT 3
Mirror
BIT 2
(bit5)
Power-Down Mode [2:0]
001 = Twos Complement
Other codes = Reserved
Other codes = Reserved
Other codes = Reserved
001 = Normal Operation
Coarse Gain
Output Format [2:0]
100 = Offset Binary
Clock Divide [2:0]
000 = Pin Control
000 = Pin Control
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
010 = Gray Code
100 = Sleep
010 = Nap
ADC01
Mirror
BIT 1
(bit6)
ADC00
(LSB)
Mirror
BIT 0
Clock
(bit7)
Edge
Next
affected by
affected by
affected by
affected by
Soft Reset
Soft Reset
Read Only
Read only
Read only
cal. value
cal. value
cal. value
cal. value
cal. value
VALUE
Reset
Reset
(Hex)
DEF.
NOT
NOT
NOT
NOT
00h
00h
00h
00h
Soft
80h
00h
00h
00h
00h
Soft
October 9, 2009
INDEXED/
GLOBAL
FN6805.3
G
G
G
G
G
G
G
G
G
G
I
I
I
I
I
I
I