KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 26

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Equivalent Circuits
INP
INN
ADDR
C6-FF
(Hex)
C0
C1
C2
C3
C4
C5
AVDD
AVDD
user_patt 1_lsb
user_patt1_msb
user_patt 2_lsb
user_patt2_msb
PARAMETER
500O Ω
FIGURE 40. ANALOG INPUTS
Reserved
reserved
NAME
test_io
Φ
F 1
Φ
F 1
26
(MSB)
BIT 7
B15
B15
User Test Mode
B7
B7
10 = Reserved
11 = Reserved
01 = Alternate
00 = Single
CSAMP
CSAMP
1.6pF
1.6pF
Φ
F 2
Φ
F 2
[1:0]
BIT 6
B14
B14
B6
B6
TABLE 17. SPI MEMORY MAP (Continued)
BIT 5
Φ
F 3
F 3
Φ
B13
B13
B5
B5
PIPELINE
PIPELINE
CHARGE
CHARGE
TO
TO
KAD5512P-50
BIT 4
B12
B12
B4
B4
Reserved
Reserved
BIT 3
2 = +FS Short
B11
B11
3 = -FS Short
1 = Midscale
B3
B3
5 = reserved
6 = reserved
4 = Checker
CLKP
CLKN
0 = Off
Board
Short
Output Test Mode [3:0]
BIT 2
B10
B10
B2
B2
AVDD
AVDD
11kO
11kO
FIGURE 41. CLOCK INPUTS
7 = One/Zero Word
BIT 1
9-15 = reserved
B1
B9
B1
B9
Ω
Ω
8 = User Input
Toggle
AVDD
18kO
18kO
(LSB)
BIT 0
B0
B8
B0
B8
Ω
Ω
AVDD
VALUE
(Hex)
DEF.
00h
00h
00h
00h
00h
00h
GENERATION
October 9, 2009
INDEXED/
CLOCK-
PHASE
GLOBAL
TO
FN6805.3
G
G
G
G
G
G