KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 4

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Absolute Maximum Ratings
AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
Electrical Specifications
DC SPECIFICATIONS
Analog Input
Full-Scale Analog Input Range
Input Resistance
Input Capacitance
Full Scale Range Temp. Drift
Input Offset Voltage
Gain Error
Common-Mode Output Voltage
Clock Inputs
Inputs Common Mode Voltage
CLKP,CLKN Input Swing
Power Requirements
1.8V Analog Supply Voltage
1.8V Digital Supply Voltage
1.8V Analog Supply Current
1.8V Digital Supply Current (Note 3)
Power Supply Rejection Ratio
Total Power Dissipation
Normal Mode
Nap Mode
Sleep Mode
Nap Mode Wakeup Time (Note 4)
Sleep Mode Wakeup Time (Note 4)
AC SPECIFICATIONS (Notes 5, 6)
Differential Nonlinearity
Integral Nonlinearity
Minimum Conversion Rate (Note 7)
Maximum Conversion Rate
1. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
PARAMETER
4
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
SYMBOL
f
IAVDD
f
OVDD
I
AVDD
PSRR
S
A
S
OVDD
V
V
DNL
V
R
C
INL
E
VTC
P
P
P
MAX
OS
CM
MIN
FS
IN
IN
G
D
D
D
KAD5512P-50
Differential
Differential
Differential
Full Temp
3mA LVDS
30MHz, 200mV
3mA LVDS
CSB at logic high
Sample Clock Running
Sample Clock Running
CONDITIONS
Thermal Information
Thermal Resistance (Typical, Note 1)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
P-P
72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
IN
= -1dBFS, f
SAMPLE
-10.0
1.40
MIN
-0.8
-2.0
435
500
1.7
1.7
KAD5512P-50
= 500MSPS.
(Note 2)
TYP
1.47
±2.0
±2.0
±0.3
±0.8
500
535
171
432
148
1.9
0.9
1.8
1.8
1.8
-36
90
68
1
1
2
MAX
1.54
10.0
635
178
460
163
1.9
1.9
0.8
2.0
76
80
6
October 9, 2009
θ
ppm/°C
JA
UNITS
MSPS
MSPS
V
LSB
LSB
mW
mW
mW
mV
mV
mA
mA
ms
pF
dB
µs
%
FN6805.3
P-P
Ω
V
V
V
V
(°C/W)
24