AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 11

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2.2
3.2.3
3.2.4
32099F–11/2010
Peripheral Functions
JTAG Port Connections
Nexus OCD AUX Port Connections
Refer to the
of the TWI, 5V Tolerant, and SMBUS pins.
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions are enabled on the same pin.
Table 3-2.
If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O
Controller configuration.
Table 3-3.
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spectively of the I/O Controller configuration. Two different OCD trace pin mappings are
possible, depending on the configuration of the OCD AXS register. For details, see the AVR32
UC Technical Reference Manual.
Table 3-4.
Function
GPIO Controller Function multiplexing
Nexus OCD AUX port connections
aWire DATAOUT
JTAG port connections
Oscillators
Pin
EVTI_N
MDO[5]
MDO[4]
MDO[3]
”TWI Pin Characteristics(1)” on page 49
48-pin
Peripheral Functions
JTAG Pinout
Nexus OCD AUX Port Connections
11
14
13
4
AXS=1
PA05
PA10
PA18
PA17
AXS=0
PB08
PB00
PB04
PB05
Description
GPIO and GPIO peripheral selection A to H
OCD trace system
aWire output in two-pin mode
JTAG debug port
OSC0, OSC32
Pin Name
PA00
PA01
PA02
PA03
for a description of the electrical properties
AT32UC3L016/32/64
JTAG Pin
TMS
TDO
TCK
TDI
11