AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 39
AT32UC3L0-XPLD
Manufacturer Part Number
AT32UC3L0-XPLD
Description
KIT DEV/EVAL FOR AT32UC3L0
Manufacturer
Atmel
Datasheet
1.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L0-XPLD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.1.3.3
32099F–11/2010
3.3V Supply Mode with 1.8V Regulated I/O Lines
In this mode, the internal regulator is connected to the 3.3V source and its output is connected
to both VDDCORE and VDDIO as shown in
use Shutdown mode.
Figure 6-4.
In this mode, some I/O lines are powered by VDDIN while other I/O lines are powered by VDDIO.
Refer to
Refer to the Power Manager chapter for a description of what parts of the system are powered in
Shutdown mode.
Important note: As the regulator has a maximum output current of 60mA, this mode can only be
used in applications where the maximum I/O current is known and compatible with the core and
peripheral power consumption. Typically, great care must be used to ensure that only a few I/O
lines are toggling at the same time and drive very small loads.
1.98-3.6V
Section 3.2 on page 9
VDDCORE
VDDANA
3.3V Supply Mode with 1.8V Regulated I/O Lines
+
-
for description of power supply for each I/O line.
VDDIN
GNDANA
I/O Pins
Linear
Figure
6-4. This configuration is required in order to
ADC
AT32UC3L016/32/64
VDDIO
Peripherals,
SCIF, BOD,
Memories,
OSC32K
RCSYS,
I/O Pins
RC32K
POR33
SM33
Wake
CPU,
DFLL
AST
GND
39
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