AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 16

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
32099F–11/2010
I/O Line Considerations
JTAG Pins
PA00
RESET_N Pin
TWI Pins PA21/PB04/PB05
TWI Pins PA05/PA07/PA17
GPIO Pins
High-Drive Pins
The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI
pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled dur-
ing reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG
pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled.
Please refer to
Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the
application.
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in
case no reset from the system needs to be applied to the product.
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-
ging, it must not be driven by external circuitry.
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the characteristics indicated in the Electrical Characteristics section. Selected pins are also
SMBus compliant (refer to
these pins provide no leakage path to ground when the AT32UC3L is powered down. This
allows other devices on the SMBus to continue communicating even though the AT32UC3L is
not powered.
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the
GPIO Module Configuration chapter for details.
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the same characteristics as other GPIO pins.
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the
GPIO Module Configuration chapter for details.
All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed
independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as
inputs with pull-up resistors disabled, except PA00. PA20 selects SCIF-RC32OUT (GPIO Func-
tion F) as default enabled after reset.
The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to
Section 7. on page 41
Section 3.2.3 on page 11
for electrical characteristics.
Section 3.2 on page
for the JTAG port connections.
9). As required by the SMBus specification,
AT32UC3L016/32/64
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