AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 80

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1.4
10.1.5
10.1.6
10.1.7
32099F–11/2010
SCIF
AST
WDT
GPIO
3. Sleepwalking in Idle and Frozen Sleep mode will mask all other PB clocks
1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
1. Reset may set status bits in the AST
2. AST wake signal is released one AST clock cycle after the BUSY bit is cleared
1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
1. Clearing GPIO interrupt may fail
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
If the CPU is in Idle or Frozen Sleep mode and a module is in a state that triggers sleep
walking, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into Idle or frozen mode.
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures.
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.
If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may
be set.
Fix/Workaround
If the part is reset and the AST is used, clear all bits in the Status Register (SR) before enter-
ing sleep mode.
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.
Writing a one to the GPIO.IFRC register to clear the interrupt will be ignored if interrupt is
enabled for the corresponding port.
AT32UC3L016/32/64
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